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mb/dell: Convert OptiPlex 9010 into directory with variants 

New boards like Dell Precision T1650 will be added as variants, in
subsequent commit. They share most of the code, except some EC
initialization tables, PCIe port configuration and subsystem ID.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I4075f0ae3b24892fcc2be07061a01f8070659239
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
This commit is contained in:
Michał Żygowski 2022-02-20 23:27:18 +01:00
parent b017a43a6d
commit 7e8b597093
26 changed files with 317 additions and 268 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/dell/optiplex_9010/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_DELL_OPTIPLEX_9010
bool "OptiPlex 9010 SFF"

28
src/mainboard/dell/optiplex_9010/Kconfig → src/mainboard/dell/snb_ivb_workstations/Kconfig
View File

@ -1,17 +1,11 @@
if BOARD_DELL_OPTIPLEX_9010 config BOARD_DELL_SNB_IVB_WORKSTATIONS
def_bool n
config IGNORE_IASL_MISSING_DEPENDENCY
def_bool y
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_12288 select BOARD_ROMSIZE_KB_12288
select HAVE_ACPI_RESUME select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select INTEL_INT15 select INTEL_INT15
select NORTHBRIDGE_INTEL_SANDYBRIDGE select NORTHBRIDGE_INTEL_SANDYBRIDGE
select SERIRQ_CONTINUOUS_MODE select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_C216
select USE_NATIVE_RAMINIT select USE_NATIVE_RAMINIT
select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_TPM1 select MAINBOARD_HAS_TPM1
@ -24,11 +18,25 @@ config BOARD_SPECIFIC_OPTIONS
select PCIEXP_L1_SUB_STATE select PCIEXP_L1_SUB_STATE
select DRIVERS_UART_8250IO select DRIVERS_UART_8250IO
if BOARD_DELL_SNB_IVB_WORKSTATIONS
config IGNORE_IASL_MISSING_DEPENDENCY
def_bool y
config MAINBOARD_DIR config MAINBOARD_DIR
default "dell/optiplex_9010" default "dell/snb_ivb_workstations"
config MAINBOARD_PART_NUMBER config MAINBOARD_PART_NUMBER
default "OptiPlex 9010" default "OptiPlex 9010" if BOARD_DELL_OPTIPLEX_9010
config VARIANT_DIR
default "optiplex_9010_sff" if BOARD_DELL_OPTIPLEX_9010
config DEVICETREE
default "variants/baseboard/devicetree.cb"
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config DRAM_RESET_GATE_GPIO config DRAM_RESET_GATE_GPIO
int int

4
src/mainboard/dell/snb_ivb_workstations/Kconfig.name Normal file
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@ -0,0 +1,4 @@
config BOARD_DELL_OPTIPLEX_9010
bool "OptiPlex 9010 SFF"
select BOARD_DELL_SNB_IVB_WORKSTATIONS
select SOUTHBRIDGE_INTEL_BD82X6X

10
src/mainboard/dell/optiplex_9010/Makefile.inc → src/mainboard/dell/snb_ivb_workstations/Makefile.inc
View File

@ -9,12 +9,20 @@ romstage-y += early_init.c
bootblock-y += sch5545_ec_early.c bootblock-y += sch5545_ec_early.c
romstage-y += sch5545_ec.c romstage-y += sch5545_ec.c
ramstage-y += sch5545_ec.c ramstage-y += sch5545_ec.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
ifeq ($(CONFIG_INCLUDE_SMSC_SCH5545_EC_FW),y) ifeq ($(CONFIG_INCLUDE_SMSC_SCH5545_EC_FW),y)
cbfs-files-y += sch5545_ecfw.bin cbfs-files-y += sch5545_ecfw.bin
sch5545_ecfw.bin-file := $(call strip_quotes,$(CONFIG_SMSC_SCH5545_EC_FW_FILE)) sch5545_ecfw.bin-file := $(call strip_quotes,$(CONFIG_SMSC_SCH5545_EC_FW_FILE))
sch5545_ecfw.bin-type := raw sch5545_ecfw.bin-type := raw
endif endif
subdirs-y += variants/baseboard
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
subdirs-y += variants/$(VARIANT_DIR)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

0
src/mainboard/dell/optiplex_9010/acpi/ec.asl → src/mainboard/dell/snb_ivb_workstations/acpi/ec.asl
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0
src/mainboard/dell/optiplex_9010/acpi/platform.asl → src/mainboard/dell/snb_ivb_workstations/acpi/platform.asl
View File

0
src/mainboard/dell/optiplex_9010/acpi/superio.asl → src/mainboard/dell/snb_ivb_workstations/acpi/superio.asl
View File

0
src/mainboard/dell/optiplex_9010/board_info.txt → src/mainboard/dell/snb_ivb_workstations/board_info.txt
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0
src/mainboard/dell/optiplex_9010/cmos.default → src/mainboard/dell/snb_ivb_workstations/cmos.default
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0
src/mainboard/dell/optiplex_9010/cmos.layout → src/mainboard/dell/snb_ivb_workstations/cmos.layout
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0
src/mainboard/dell/optiplex_9010/dsdt.asl → src/mainboard/dell/snb_ivb_workstations/dsdt.asl
View File

2
src/mainboard/dell/optiplex_9010/early_init.c → src/mainboard/dell/snb_ivb_workstations/early_init.c
View File

@ -7,7 +7,7 @@
#include <superio/smsc/sch5545/sch5545.h> #include <superio/smsc/sch5545/sch5545.h>
#include <superio/smsc/sch5545/sch5545_emi.h> #include <superio/smsc/sch5545/sch5545_emi.h>
#include "sch5545_ec.h" #include <baseboard/sch5545_ec.h>
const struct southbridge_usb_port mainboard_usb_ports[] = { const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 6, 0 }, { 1, 6, 0 },

0
src/mainboard/dell/optiplex_9010/gma-mainboard.ads → src/mainboard/dell/snb_ivb_workstations/gma-mainboard.ads
View File

0
src/mainboard/dell/optiplex_9010/gpio.c → src/mainboard/dell/snb_ivb_workstations/gpio.c
View File

0
src/mainboard/dell/snb_ivb_workstations/hda_verb.c Normal file
View File

7
src/mainboard/dell/optiplex_9010/mainboard.c → src/mainboard/dell/snb_ivb_workstations/mainboard.c
View File

@ -9,7 +9,7 @@
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <superio/smsc/sch5545/sch5545.h> #include <superio/smsc/sch5545/sch5545.h>
#include "sch5545_ec.h" #include <baseboard/sch5545_ec.h>
#define SIO_PORT 0x2e #define SIO_PORT 0x2e
@ -64,13 +64,16 @@ static void mainboard_enable(struct device *dev)
printk(BIOS_DEBUG, "Chassis type: "); printk(BIOS_DEBUG, "Chassis type: ");
switch (pin_sts) { switch (pin_sts) {
case 0: case 0:
case 4:
printk(BIOS_DEBUG, "MT\n"); printk(BIOS_DEBUG, "MT\n");
break; break;
case 3: case 3:
case 11: case 11:
printk(BIOS_DEBUG, "USFF\n"); printk(BIOS_DEBUG, "USFF\n");
break; break;
case 4:
/* As per table in schematics, but don't know what this is */
printk(BIOS_DEBUG, "Comoros\n");
break;
case 1: case 1:
case 9: case 9:
case 5: case 5:

2
src/mainboard/dell/optiplex_9010/romstage.c → src/mainboard/dell/snb_ivb_workstations/romstage.c
View File

@ -10,7 +10,7 @@
#include <superio/smsc/sch5545/sch5545.h> #include <superio/smsc/sch5545/sch5545.h>
#include <superio/smsc/sch5545/sch5545_emi.h> #include <superio/smsc/sch5545/sch5545_emi.h>
#include "sch5545_ec.h" #include <baseboard/sch5545_ec.h>
void mainboard_late_rcba_config(void) void mainboard_late_rcba_config(void)
{ {

246
src/mainboard/dell/optiplex_9010/sch5545_ec.c → src/mainboard/dell/snb_ivb_workstations/sch5545_ec.c
View File

@ -10,25 +10,14 @@
#include <superio/smsc/sch5545/sch5545.h> #include <superio/smsc/sch5545/sch5545.h>
#include <superio/smsc/sch5545/sch5545_emi.h> #include <superio/smsc/sch5545/sch5545_emi.h>
#include "sch5545_ec.h" #include <baseboard/sch5545_ec.h>
#include <variant/sch5545_ec_tables.h>
#define GPIO_CHASSIS_ID0 1 #define GPIO_CHASSIS_ID0 1
#define GPIO_CHASSIS_ID1 17 #define GPIO_CHASSIS_ID1 17
#define GPIO_CHASSIS_ID2 37 #define GPIO_CHASSIS_ID2 37
#define GPIO_FRONT_PANEL_CHASSIS_DET_L 70 #define GPIO_FRONT_PANEL_CHASSIS_DET_L 70
enum {
TDP_16 = 0x10,
TDP_32 = 0x20,
TDP_COMMON = 0xff,
};
typedef struct ec_val_reg_tdp {
uint8_t val;
uint16_t reg;
uint8_t tdp;
} ec_chassis_tdp_t;
static const struct ec_val_reg ec_hwm_init_seq[] = { static const struct ec_val_reg ec_hwm_init_seq[] = {
{ 0xa0, 0x02fc }, { 0xa0, 0x02fc },
{ 0x32, 0x02fd }, { 0x32, 0x02fd },
@ -105,234 +94,6 @@ static const struct ec_val_reg ec_hwm_init_seq[] = {
{ 0x03, 0x0071 }, { 0x03, 0x0071 },
}; };
static const ec_chassis_tdp_t ec_hwm_chassis3[] = {
{ 0x33, 0x0005, TDP_COMMON },
{ 0x2f, 0x0018, TDP_COMMON },
{ 0x2f, 0x0019, TDP_COMMON },
{ 0x2f, 0x001a, TDP_COMMON },
{ 0x00, 0x0080, TDP_COMMON },
{ 0x00, 0x0081, TDP_COMMON },
{ 0xbb, 0x0083, TDP_COMMON },
{ 0x8a, 0x0085, TDP_16 },
{ 0x2c, 0x0086, TDP_16 },
{ 0x66, 0x008a, TDP_16 },
{ 0x5b, 0x008b, TDP_16 },
{ 0x65, 0x0090, TDP_COMMON },
{ 0x70, 0x0091, TDP_COMMON },
{ 0x86, 0x0092, TDP_COMMON },
{ 0xa4, 0x0096, TDP_COMMON },
{ 0xa4, 0x0097, TDP_COMMON },
{ 0xa4, 0x0098, TDP_COMMON },
{ 0xa4, 0x009b, TDP_COMMON },
{ 0x0e, 0x00a0, TDP_COMMON },
{ 0x0e, 0x00a1, TDP_COMMON },
{ 0x7c, 0x00ae, TDP_COMMON },
{ 0x86, 0x00af, TDP_COMMON },
{ 0x95, 0x00b0, TDP_COMMON },
{ 0x9a, 0x00b3, TDP_COMMON },
{ 0x08, 0x00b6, TDP_COMMON },
{ 0x08, 0x00b7, TDP_COMMON },
{ 0x64, 0x00ea, TDP_COMMON },
{ 0xff, 0x00ef, TDP_COMMON },
{ 0x15, 0x00f8, TDP_COMMON },
{ 0x00, 0x00f9, TDP_COMMON },
{ 0x30, 0x00f0, TDP_COMMON },
{ 0x01, 0x00fd, TDP_COMMON },
{ 0x88, 0x01a1, TDP_COMMON },
{ 0x08, 0x01a2, TDP_COMMON },
{ 0x08, 0x01b1, TDP_COMMON },
{ 0x94, 0x01be, TDP_COMMON },
{ 0x94, 0x0280, TDP_16 },
{ 0x11, 0x0281, TDP_16 },
{ 0x03, 0x0282, TDP_COMMON },
{ 0x0a, 0x0283, TDP_COMMON },
{ 0x80, 0x0284, TDP_COMMON },
{ 0x03, 0x0285, TDP_COMMON },
{ 0x68, 0x0288, TDP_16 },
{ 0x10, 0x0289, TDP_16 },
{ 0x03, 0x028a, TDP_COMMON },
{ 0x0a, 0x028b, TDP_COMMON },
{ 0x80, 0x028c, TDP_COMMON },
{ 0x03, 0x028d, TDP_COMMON },
};
static const ec_chassis_tdp_t ec_hwm_chassis4[] = {
{ 0x33, 0x0005, TDP_COMMON },
{ 0x2f, 0x0018, TDP_COMMON },
{ 0x2f, 0x0019, TDP_COMMON },
{ 0x2f, 0x001a, TDP_COMMON },
{ 0x00, 0x0080, TDP_COMMON },
{ 0x00, 0x0081, TDP_COMMON },
{ 0xbb, 0x0083, TDP_COMMON },
{ 0x99, 0x0085, TDP_32 },
{ 0x98, 0x0085, TDP_16 },
{ 0xbc, 0x0086, TDP_32 },
{ 0x1c, 0x0086, TDP_16 },
{ 0x39, 0x008a, TDP_32 },
{ 0x3d, 0x008a, TDP_16 },
{ 0x40, 0x008b, TDP_32 },
{ 0x43, 0x008b, TDP_16 },
{ 0x68, 0x0090, TDP_COMMON },
{ 0x5e, 0x0091, TDP_COMMON },
{ 0x86, 0x0092, TDP_COMMON },
{ 0xa4, 0x0096, TDP_COMMON },
{ 0xa4, 0x0097, TDP_COMMON },
{ 0xa4, 0x0098, TDP_COMMON },
{ 0xa4, 0x009b, TDP_COMMON },
{ 0x0c, 0x00a0, TDP_COMMON },
{ 0x0c, 0x00a1, TDP_COMMON },
{ 0x72, 0x00ae, TDP_COMMON },
{ 0x7c, 0x00af, TDP_COMMON },
{ 0x9a, 0x00b0, TDP_COMMON },
{ 0x7c, 0x00b3, TDP_COMMON },
{ 0x08, 0x00b6, TDP_COMMON },
{ 0x08, 0x00b7, TDP_COMMON },
{ 0x64, 0x00ea, TDP_COMMON },
{ 0xff, 0x00ef, TDP_COMMON },
{ 0x15, 0x00f8, TDP_COMMON },
{ 0x00, 0x00f9, TDP_COMMON },
{ 0x30, 0x00f0, TDP_COMMON },
{ 0x01, 0x00fd, TDP_COMMON },
{ 0x88, 0x01a1, TDP_COMMON },
{ 0x08, 0x01a2, TDP_COMMON },
{ 0x08, 0x01b1, TDP_COMMON },
{ 0x90, 0x01be, TDP_COMMON },
{ 0x94, 0x0280, TDP_32 },
{ 0x11, 0x0281, TDP_32 },
{ 0x68, 0x0280, TDP_16 },
{ 0x10, 0x0281, TDP_16 },
{ 0x03, 0x0282, TDP_COMMON },
{ 0x0a, 0x0283, TDP_COMMON },
{ 0x80, 0x0284, TDP_COMMON },
{ 0x03, 0x0285, TDP_COMMON },
{ 0xa0, 0x0288, TDP_32 },
{ 0x0f, 0x0289, TDP_32 },
{ 0xd8, 0x0288, TDP_16 },
{ 0x0e, 0x0289, TDP_16 },
{ 0x03, 0x028a, TDP_COMMON },
{ 0x0a, 0x028b, TDP_COMMON },
{ 0x80, 0x028c, TDP_COMMON },
{ 0x03, 0x028d, TDP_COMMON },
};
static const ec_chassis_tdp_t ec_hwm_chassis5[] = {
{ 0x33, 0x0005, TDP_COMMON },
{ 0x2f, 0x0018, TDP_COMMON },
{ 0x2f, 0x0019, TDP_COMMON },
{ 0x2f, 0x001a, TDP_COMMON },
{ 0x00, 0x0080, TDP_COMMON },
{ 0x00, 0x0081, TDP_COMMON },
{ 0xbb, 0x0083, TDP_COMMON },
{ 0x89, 0x0085, TDP_32 },
{ 0x99, 0x0085, TDP_16 },
{ 0x9c, 0x0086, TDP_COMMON },
{ 0x39, 0x008a, TDP_32 },
{ 0x42, 0x008a, TDP_16 },
{ 0x6b, 0x008b, TDP_32 },
{ 0x74, 0x008b, TDP_16 },
{ 0x5e, 0x0091, TDP_COMMON },
{ 0x86, 0x0092, TDP_COMMON },
{ 0xa4, 0x0096, TDP_COMMON },
{ 0xa4, 0x0097, TDP_COMMON },
{ 0xa4, 0x0098, TDP_COMMON },
{ 0xa4, 0x009b, TDP_COMMON },
{ 0x0c, 0x00a0, TDP_COMMON },
{ 0x0c, 0x00a1, TDP_COMMON },
{ 0x7c, 0x00ae, TDP_COMMON },
{ 0x7c, 0x00af, TDP_COMMON },
{ 0x9a, 0x00b0, TDP_COMMON },
{ 0x7c, 0x00b3, TDP_COMMON },
{ 0x08, 0x00b6, TDP_COMMON },
{ 0x08, 0x00b7, TDP_COMMON },
{ 0x64, 0x00ea, TDP_COMMON },
{ 0xff, 0x00ef, TDP_COMMON },
{ 0x15, 0x00f8, TDP_COMMON },
{ 0x00, 0x00f9, TDP_COMMON },
{ 0x30, 0x00f0, TDP_COMMON },
{ 0x01, 0x00fd, TDP_COMMON },
{ 0x88, 0x01a1, TDP_COMMON },
{ 0x08, 0x01a2, TDP_COMMON },
{ 0x08, 0x01b1, TDP_COMMON },
{ 0x90, 0x01be, TDP_COMMON },
{ 0x94, 0x0280, TDP_32 },
{ 0x11, 0x0281, TDP_32 },
{ 0x3c, 0x0280, TDP_16 },
{ 0x0f, 0x0281, TDP_16 },
{ 0x03, 0x0282, TDP_COMMON },
{ 0x0a, 0x0283, TDP_COMMON },
{ 0x80, 0x0284, TDP_COMMON },
{ 0x03, 0x0285, TDP_COMMON },
{ 0x60, 0x0288, TDP_32 },
{ 0x09, 0x0289, TDP_32 },
{ 0x98, 0x0288, TDP_16 },
{ 0x08, 0x0289, TDP_16 },
{ 0x03, 0x028a, TDP_COMMON },
{ 0x0a, 0x028b, TDP_COMMON },
{ 0x80, 0x028c, TDP_COMMON },
{ 0x03, 0x028d, TDP_COMMON },
};
static const ec_chassis_tdp_t ec_hwm_chassis6[] = {
{ 0x33, 0x0005, TDP_COMMON },
{ 0x2f, 0x0018, TDP_COMMON },
{ 0x2f, 0x0019, TDP_COMMON },
{ 0x2f, 0x001a, TDP_COMMON },
{ 0x00, 0x0080, TDP_COMMON },
{ 0x00, 0x0081, TDP_COMMON },
{ 0xbb, 0x0083, TDP_COMMON },
{ 0x99, 0x0085, TDP_32 },
{ 0x98, 0x0085, TDP_16 },
{ 0xdc, 0x0086, TDP_32 },
{ 0x9c, 0x0086, TDP_16 },
{ 0x3d, 0x008a, TDP_32 },
{ 0x43, 0x008a, TDP_16 },
{ 0x4e, 0x008b, TDP_32 },
{ 0x47, 0x008b, TDP_16 },
{ 0x6d, 0x0090, TDP_COMMON },
{ 0x5f, 0x0091, TDP_32 },
{ 0x61, 0x0091, TDP_16 },
{ 0x86, 0x0092, TDP_COMMON },
{ 0xa4, 0x0096, TDP_COMMON },
{ 0xa4, 0x0097, TDP_COMMON },
{ 0xa4, 0x0098, TDP_COMMON },
{ 0xa4, 0x009b, TDP_COMMON },
{ 0x0e, 0x00a0, TDP_COMMON },
{ 0x0e, 0x00a1, TDP_COMMON },
{ 0x7c, 0x00ae, TDP_COMMON },
{ 0x7c, 0x00af, TDP_COMMON },
{ 0x98, 0x00b0, TDP_32 },
{ 0x9a, 0x00b0, TDP_16 },
{ 0x9a, 0x00b3, TDP_COMMON },
{ 0x08, 0x00b6, TDP_COMMON },
{ 0x08, 0x00b7, TDP_COMMON },
{ 0x64, 0x00ea, TDP_COMMON },
{ 0xff, 0x00ef, TDP_COMMON },
{ 0x15, 0x00f8, TDP_COMMON },
{ 0x00, 0x00f9, TDP_COMMON },
{ 0x30, 0x00f0, TDP_COMMON },
{ 0x01, 0x00fd, TDP_COMMON },
{ 0x88, 0x01a1, TDP_COMMON },
{ 0x08, 0x01a2, TDP_COMMON },
{ 0x08, 0x01b1, TDP_COMMON },
{ 0x97, 0x01be, TDP_32 },
{ 0x95, 0x01be, TDP_16 },
{ 0x68, 0x0280, TDP_32 },
{ 0x10, 0x0281, TDP_32 },
{ 0xd8, 0x0280, TDP_16 },
{ 0x0e, 0x0281, TDP_16 },
{ 0x03, 0x0282, TDP_COMMON },
{ 0x0a, 0x0283, TDP_COMMON },
{ 0x80, 0x0284, TDP_COMMON },
{ 0x03, 0x0285, TDP_COMMON },
{ 0xe4, 0x0288, TDP_32 },
{ 0x0c, 0x0289, TDP_32 },
{ 0x10, 0x0288, TDP_16 },
{ 0x0e, 0x0289, TDP_16 },
{ 0x03, 0x028a, TDP_COMMON },
{ 0x0a, 0x028b, TDP_COMMON },
{ 0x80, 0x028c, TDP_COMMON },
{ 0x03, 0x028d, TDP_COMMON },
};
static uint8_t send_mbox_msg_with_int(uint8_t mbox_message) static uint8_t send_mbox_msg_with_int(uint8_t mbox_message)
{ {
@ -617,12 +378,14 @@ void sch5545_ec_hwm_init(void *unused)
ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP); ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP);
val |= 0x02; val |= 0x02;
ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP); ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP);
ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP); ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP);
ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP); ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP);
ec_read_write_reg(EC_HWM_LDN, 0x0042, &val, READ_OP); ec_read_write_reg(EC_HWM_LDN, 0x0042, &val, READ_OP);
ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP); ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP);
val |= 0x04; val |= 0x04;
ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP); ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP);
ec_read_write_reg(EC_HWM_LDN, 0x0081, &val, READ_OP); ec_read_write_reg(EC_HWM_LDN, 0x0081, &val, READ_OP);
ec_read_write_reg(EC_HWM_LDN, 0x0027, &val, READ_OP); ec_read_write_reg(EC_HWM_LDN, 0x0027, &val, READ_OP);
@ -672,6 +435,7 @@ void sch5545_ec_hwm_init(void *unused)
ec_read_write_reg(EC_HWM_LDN, 0x00b8, &val, READ_OP); ec_read_write_reg(EC_HWM_LDN, 0x00b8, &val, READ_OP);
if (chassis_type == 4 || chassis_type == 5) { if (chassis_type == 4 || chassis_type == 5) {
ec_read_write_reg(EC_HWM_LDN, 0x0027, &val, READ_OP); ec_read_write_reg(EC_HWM_LDN, 0x0027, &val, READ_OP);
if (val == 0) { if (val == 0) {

2
src/mainboard/dell/optiplex_9010/sch5545_ec_early.c → src/mainboard/dell/snb_ivb_workstations/sch5545_ec_early.c
View File

@ -4,7 +4,7 @@
#include <superio/smsc/sch5545/sch5545.h> #include <superio/smsc/sch5545/sch5545.h>
#include <superio/smsc/sch5545/sch5545_emi.h> #include <superio/smsc/sch5545/sch5545_emi.h>
#include "sch5545_ec.h" #include <baseboard/sch5545_ec.h>
static uint16_t emi_bar; static uint16_t emi_bar;

0
src/mainboard/dell/optiplex_9010/smihandler.c → src/mainboard/dell/snb_ivb_workstations/smihandler.c
View File

14
src/mainboard/dell/optiplex_9010/devicetree.cb → src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb
View File

@ -10,11 +10,10 @@ chip northbridge/intel/sandybridge
end end
end end
device domain 0 on device domain 0 on
subsystemid 0x1028 0x052c inherit
device pci 00.0 on end # Host bridge Host bridge device pci 00.0 on end # Host bridge Host bridge
device pci 01.0 on # PEG1 (blue slot1) device pci 01.0 on # PEG1 (blue slot1)
smbios_slot_desc "0xB6" "4" "SLOT1" "0x0D" smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "SLOT1" "SlotDataBusWidth16X"
end end
device pci 02.0 on end # Internal graphics VGA controller device pci 02.0 on end # Internal graphics VGA controller
device pci 06.0 off end # PEG2 device pci 06.0 off end # PEG2
@ -30,7 +29,6 @@ chip northbridge/intel/sandybridge
register "gen4_dec" = "0x001c0901" register "gen4_dec" = "0x001c0901"
register "pcie_port_coalesce" = "true" register "pcie_port_coalesce" = "true"
register "sata_interface_speed_support" = "0x3" register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x7"
register "spi_lvscc" = "0x2005" register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005" register "spi_uvscc" = "0x2005"
register "superspeed_capable_ports" = "0x0000000f" register "superspeed_capable_ports" = "0x0000000f"
@ -48,12 +46,10 @@ chip northbridge/intel/sandybridge
device pci 1c.1 off end # PCIe Port #2 device pci 1c.1 off end # PCIe Port #2
device pci 1c.2 off end # PCIe Port #3 device pci 1c.2 off end # PCIe Port #3
device pci 1c.3 off end # PCIe Port #4 device pci 1c.3 off end # PCIe Port #4
device pci 1c.4 on # PCIe Port #5 device pci 1c.4 off end # PCIe Port #5
smbios_slot_desc "0xB6" "4" "SLOT2" "0x0A" device pci 1c.5 off end # PCIe Port #6
end device pci 1c.6 off end # PCIe Port #7
device pci 1c.5 on end # PCIe Port #6 device pci 1c.7 off end # PCIe Port #8
device pci 1c.6 on end # PCIe Port #7
device pci 1c.7 on end # PCIe Port #8
device pci 1d.0 on end # USB2 EHCI #1 device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge device pci 1e.0 off end # PCI bridge
device pci 1f.0 on # LPC bridge device pci 1f.0 on # LPC bridge

17
src/mainboard/dell/optiplex_9010/sch5545_ec.h → src/mainboard/dell/snb_ivb_workstations/variants/baseboard/include/baseboard/sch5545_ec.h
View File

@ -1,5 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#ifndef SCH5545_BOARD_EC_H
#define SCH5545_BOARD_EC_H
#include <stdint.h> #include <stdint.h>
#define READ_OP 0 #define READ_OP 0
@ -21,8 +24,22 @@ struct ec_val_reg {
uint16_t reg; uint16_t reg;
}; };
enum {
TDP_16 = 0x10,
TDP_32 = 0x20,
TDP_COMMON = 0xff,
};
typedef struct ec_val_reg_tdp {
uint8_t val;
uint16_t reg;
uint8_t tdp;
} ec_chassis_tdp_t;
uint16_t sch5545_get_ec_fw_version(void); uint16_t sch5545_get_ec_fw_version(void);
void sch5545_update_ec_firmware(uint16_t ec_version); void sch5545_update_ec_firmware(uint16_t ec_version);
void sch5545_ec_early_init(void); void sch5545_ec_early_init(void);
void sch5545_ec_hwm_early_init(void); void sch5545_ec_hwm_early_init(void);
void sch5545_ec_hwm_init(void *unused); void sch5545_ec_hwm_init(void *unused);
#endif // SCH5545_BOARD_EC_H

0
src/mainboard/dell/optiplex_9010/data.vbt → src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/data.vbt
View File

0
src/mainboard/dell/optiplex_9010/hda_verb.c → src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/hda_verb.c
View File

237
src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/include/variant/sch5545_ec_tables.h Normal file
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@ -0,0 +1,237 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef SCH5545_BOARD_EC_TABLE_H
#define SCH5545_BOARD_EC_TABLE_H
#include <baseboard/sch5545_ec.h>
static const ec_chassis_tdp_t ec_hwm_chassis3[] = {
{ 0x33, 0x0005, TDP_COMMON },
{ 0x2f, 0x0018, TDP_COMMON },
{ 0x2f, 0x0019, TDP_COMMON },
{ 0x2f, 0x001a, TDP_COMMON },
{ 0x00, 0x0080, TDP_COMMON },
{ 0x00, 0x0081, TDP_COMMON },
{ 0xbb, 0x0083, TDP_COMMON },
{ 0x8a, 0x0085, TDP_16 },
{ 0x2c, 0x0086, TDP_16 },
{ 0x66, 0x008a, TDP_16 },
{ 0x5b, 0x008b, TDP_16 },
{ 0x65, 0x0090, TDP_COMMON },
{ 0x70, 0x0091, TDP_COMMON },
{ 0x86, 0x0092, TDP_COMMON },
{ 0xa4, 0x0096, TDP_COMMON },
{ 0xa4, 0x0097, TDP_COMMON },
{ 0xa4, 0x0098, TDP_COMMON },
{ 0xa4, 0x009b, TDP_COMMON },
{ 0x0e, 0x00a0, TDP_COMMON },
{ 0x0e, 0x00a1, TDP_COMMON },
{ 0x7c, 0x00ae, TDP_COMMON },
{ 0x86, 0x00af, TDP_COMMON },
{ 0x95, 0x00b0, TDP_COMMON },
{ 0x9a, 0x00b3, TDP_COMMON },
{ 0x08, 0x00b6, TDP_COMMON },
{ 0x08, 0x00b7, TDP_COMMON },
{ 0x64, 0x00ea, TDP_COMMON },
{ 0xff, 0x00ef, TDP_COMMON },
{ 0x15, 0x00f8, TDP_COMMON },
{ 0x00, 0x00f9, TDP_COMMON },
{ 0x30, 0x00f0, TDP_COMMON },
{ 0x01, 0x00fd, TDP_COMMON },
{ 0x88, 0x01a1, TDP_COMMON },
{ 0x08, 0x01a2, TDP_COMMON },
{ 0x08, 0x01b1, TDP_COMMON },
{ 0x94, 0x01be, TDP_COMMON },
{ 0x94, 0x0280, TDP_16 },
{ 0x11, 0x0281, TDP_16 },
{ 0x03, 0x0282, TDP_COMMON },
{ 0x0a, 0x0283, TDP_COMMON },
{ 0x80, 0x0284, TDP_COMMON },
{ 0x03, 0x0285, TDP_COMMON },
{ 0x68, 0x0288, TDP_16 },
{ 0x10, 0x0289, TDP_16 },
{ 0x03, 0x028a, TDP_COMMON },
{ 0x0a, 0x028b, TDP_COMMON },
{ 0x80, 0x028c, TDP_COMMON },
{ 0x03, 0x028d, TDP_COMMON },
};
static const ec_chassis_tdp_t ec_hwm_chassis4[] = {
{ 0x33, 0x0005, TDP_COMMON },
{ 0x2f, 0x0018, TDP_COMMON },
{ 0x2f, 0x0019, TDP_COMMON },
{ 0x2f, 0x001a, TDP_COMMON },
{ 0x00, 0x0080, TDP_COMMON },
{ 0x00, 0x0081, TDP_COMMON },
{ 0xbb, 0x0083, TDP_COMMON },
{ 0x99, 0x0085, TDP_32 },
{ 0x98, 0x0085, TDP_16 },
{ 0xbc, 0x0086, TDP_32 },
{ 0x1c, 0x0086, TDP_16 },
{ 0x39, 0x008a, TDP_32 },
{ 0x3d, 0x008a, TDP_16 },
{ 0x40, 0x008b, TDP_32 },
{ 0x43, 0x008b, TDP_16 },
{ 0x68, 0x0090, TDP_COMMON },
{ 0x5e, 0x0091, TDP_COMMON },
{ 0x86, 0x0092, TDP_COMMON },
{ 0xa4, 0x0096, TDP_COMMON },
{ 0xa4, 0x0097, TDP_COMMON },
{ 0xa4, 0x0098, TDP_COMMON },
{ 0xa4, 0x009b, TDP_COMMON },
{ 0x0c, 0x00a0, TDP_COMMON },
{ 0x0c, 0x00a1, TDP_COMMON },
{ 0x72, 0x00ae, TDP_COMMON },
{ 0x7c, 0x00af, TDP_COMMON },
{ 0x9a, 0x00b0, TDP_COMMON },
{ 0x7c, 0x00b3, TDP_COMMON },
{ 0x08, 0x00b6, TDP_COMMON },
{ 0x08, 0x00b7, TDP_COMMON },
{ 0x64, 0x00ea, TDP_COMMON },
{ 0xff, 0x00ef, TDP_COMMON },
{ 0x15, 0x00f8, TDP_COMMON },
{ 0x00, 0x00f9, TDP_COMMON },
{ 0x30, 0x00f0, TDP_COMMON },
{ 0x01, 0x00fd, TDP_COMMON },
{ 0x88, 0x01a1, TDP_COMMON },
{ 0x08, 0x01a2, TDP_COMMON },
{ 0x08, 0x01b1, TDP_COMMON },
{ 0x90, 0x01be, TDP_COMMON },
{ 0x94, 0x0280, TDP_32 },
{ 0x11, 0x0281, TDP_32 },
{ 0x68, 0x0280, TDP_16 },
{ 0x10, 0x0281, TDP_16 },
{ 0x03, 0x0282, TDP_COMMON },
{ 0x0a, 0x0283, TDP_COMMON },
{ 0x80, 0x0284, TDP_COMMON },
{ 0x03, 0x0285, TDP_COMMON },
{ 0xa0, 0x0288, TDP_32 },
{ 0x0f, 0x0289, TDP_32 },
{ 0xd8, 0x0288, TDP_16 },
{ 0x0e, 0x0289, TDP_16 },
{ 0x03, 0x028a, TDP_COMMON },
{ 0x0a, 0x028b, TDP_COMMON },
{ 0x80, 0x028c, TDP_COMMON },
{ 0x03, 0x028d, TDP_COMMON },
};
static const ec_chassis_tdp_t ec_hwm_chassis5[] = {
{ 0x33, 0x0005, TDP_COMMON },
{ 0x2f, 0x0018, TDP_COMMON },
{ 0x2f, 0x0019, TDP_COMMON },
{ 0x2f, 0x001a, TDP_COMMON },
{ 0x00, 0x0080, TDP_COMMON },
{ 0x00, 0x0081, TDP_COMMON },
{ 0xbb, 0x0083, TDP_COMMON },
{ 0x89, 0x0085, TDP_32 },
{ 0x99, 0x0085, TDP_16 },
{ 0x9c, 0x0086, TDP_COMMON },
{ 0x39, 0x008a, TDP_32 },
{ 0x42, 0x008a, TDP_16 },
{ 0x6b, 0x008b, TDP_32 },
{ 0x74, 0x008b, TDP_16 },
{ 0x5e, 0x0091, TDP_COMMON },
{ 0x86, 0x0092, TDP_COMMON },
{ 0xa4, 0x0096, TDP_COMMON },
{ 0xa4, 0x0097, TDP_COMMON },
{ 0xa4, 0x0098, TDP_COMMON },
{ 0xa4, 0x009b, TDP_COMMON },
{ 0x0c, 0x00a0, TDP_COMMON },
{ 0x0c, 0x00a1, TDP_COMMON },
{ 0x7c, 0x00ae, TDP_COMMON },
{ 0x7c, 0x00af, TDP_COMMON },
{ 0x9a, 0x00b0, TDP_COMMON },
{ 0x7c, 0x00b3, TDP_COMMON },
{ 0x08, 0x00b6, TDP_COMMON },
{ 0x08, 0x00b7, TDP_COMMON },
{ 0x64, 0x00ea, TDP_COMMON },
{ 0xff, 0x00ef, TDP_COMMON },
{ 0x15, 0x00f8, TDP_COMMON },
{ 0x00, 0x00f9, TDP_COMMON },
{ 0x30, 0x00f0, TDP_COMMON },
{ 0x01, 0x00fd, TDP_COMMON },
{ 0x88, 0x01a1, TDP_COMMON },
{ 0x08, 0x01a2, TDP_COMMON },
{ 0x08, 0x01b1, TDP_COMMON },
{ 0x90, 0x01be, TDP_COMMON },
{ 0x94, 0x0280, TDP_32 },
{ 0x11, 0x0281, TDP_32 },
{ 0x3c, 0x0280, TDP_16 },
{ 0x0f, 0x0281, TDP_16 },
{ 0x03, 0x0282, TDP_COMMON },
{ 0x0a, 0x0283, TDP_COMMON },
{ 0x80, 0x0284, TDP_COMMON },
{ 0x03, 0x0285, TDP_COMMON },
{ 0x60, 0x0288, TDP_32 },
{ 0x09, 0x0289, TDP_32 },
{ 0x98, 0x0288, TDP_16 },
{ 0x08, 0x0289, TDP_16 },
{ 0x03, 0x028a, TDP_COMMON },
{ 0x0a, 0x028b, TDP_COMMON },
{ 0x80, 0x028c, TDP_COMMON },
{ 0x03, 0x028d, TDP_COMMON },
};
static const ec_chassis_tdp_t ec_hwm_chassis6[] = {
{ 0x33, 0x0005, TDP_COMMON },
{ 0x2f, 0x0018, TDP_COMMON },
{ 0x2f, 0x0019, TDP_COMMON },
{ 0x2f, 0x001a, TDP_COMMON },
{ 0x00, 0x0080, TDP_COMMON },
{ 0x00, 0x0081, TDP_COMMON },
{ 0xbb, 0x0083, TDP_COMMON },
{ 0x99, 0x0085, TDP_32 },
{ 0x98, 0x0085, TDP_16 },
{ 0xdc, 0x0086, TDP_32 },
{ 0x9c, 0x0086, TDP_16 },
{ 0x3d, 0x008a, TDP_32 },
{ 0x43, 0x008a, TDP_16 },
{ 0x4e, 0x008b, TDP_32 },
{ 0x47, 0x008b, TDP_16 },
{ 0x6d, 0x0090, TDP_COMMON },
{ 0x5f, 0x0091, TDP_32 },
{ 0x61, 0x0091, TDP_16 },
{ 0x86, 0x0092, TDP_COMMON },
{ 0xa4, 0x0096, TDP_COMMON },
{ 0xa4, 0x0097, TDP_COMMON },
{ 0xa4, 0x0098, TDP_COMMON },
{ 0xa4, 0x009b, TDP_COMMON },
{ 0x0e, 0x00a0, TDP_COMMON },
{ 0x0e, 0x00a1, TDP_COMMON },
{ 0x7c, 0x00ae, TDP_COMMON },
{ 0x7c, 0x00af, TDP_COMMON },
{ 0x98, 0x00b0, TDP_32 },
{ 0x9a, 0x00b0, TDP_16 },
{ 0x9a, 0x00b3, TDP_COMMON },
{ 0x08, 0x00b6, TDP_COMMON },
{ 0x08, 0x00b7, TDP_COMMON },
{ 0x64, 0x00ea, TDP_COMMON },
{ 0xff, 0x00ef, TDP_COMMON },
{ 0x15, 0x00f8, TDP_COMMON },
{ 0x00, 0x00f9, TDP_COMMON },
{ 0x30, 0x00f0, TDP_COMMON },
{ 0x01, 0x00fd, TDP_COMMON },
{ 0x88, 0x01a1, TDP_COMMON },
{ 0x08, 0x01a2, TDP_COMMON },
{ 0x08, 0x01b1, TDP_COMMON },
{ 0x97, 0x01be, TDP_32 },
{ 0x95, 0x01be, TDP_16 },
{ 0x68, 0x0280, TDP_32 },
{ 0x10, 0x0281, TDP_32 },
{ 0xd8, 0x0280, TDP_16 },
{ 0x0e, 0x0281, TDP_16 },
{ 0x03, 0x0282, TDP_COMMON },
{ 0x0a, 0x0283, TDP_COMMON },
{ 0x80, 0x0284, TDP_COMMON },
{ 0x03, 0x0285, TDP_COMMON },
{ 0xe4, 0x0288, TDP_32 },
{ 0x0c, 0x0289, TDP_32 },
{ 0x10, 0x0288, TDP_16 },
{ 0x0e, 0x0289, TDP_16 },
{ 0x03, 0x028a, TDP_COMMON },
{ 0x0a, 0x028b, TDP_COMMON },
{ 0x80, 0x028c, TDP_COMMON },
{ 0x03, 0x028d, TDP_COMMON },
};
#endif // SCH5545_BOARD_EC_TABLE_H

14
src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb Normal file
View File

@ -0,0 +1,14 @@
chip northbridge/intel/sandybridge
device domain 0 on
subsystemid 0x1028 0x052c inherit
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "sata_port_map" = "0x7"
device pci 1c.4 on # PCIe Port #5
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "SLOT2" "SlotDataBusWidth4X"
end
device pci 1c.5 on end # PCIe Port #6
device pci 1c.6 on end # PCIe Port #7
device pci 1c.7 on end # PCIe Port #8
end
end
end