soc/amd/cezanne/acpi/pci0.asl: Add LPC device

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iadb8e77fb618e14cd9a6c0214bb3f5ae2dbc829d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/soc/amd/cezanne/acpi/pci0.asl

@@ -78,4 +78,7 @@ Device(PCI0) {
 		Return(CRES) /* note to change the Name buffer */
 	} /* end of Method(_SB.PCI0._CRS) */
 
+	/* 0:14.3 - LPC */
+	#include <soc/amd/common/acpi/lpc.asl>
+
 } /* End PCI0 scope */