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soc/amd/cezanne/acpi/pci0.asl: Add LPC device 

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iadb8e77fb618e14cd9a6c0214bb3f5ae2dbc829d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Raul E Rangel 2021-02-19 08:59:01 -07:00 committed by Felix Held
parent 56823f53dc
commit 7e96518e63
1 changed files with 3 additions and 0 deletions
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src/soc/amd/cezanne/acpi/pci0.asl
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@ -78,4 +78,7 @@ Device(PCI0) {
Return(CRES) /* note to change the Name buffer */ Return(CRES) /* note to change the Name buffer */
} /* end of Method(_SB.PCI0._CRS) */ } /* end of Method(_SB.PCI0._CRS) */
/* 0:14.3 - LPC */
#include <soc/amd/common/acpi/lpc.asl>
} /* End PCI0 scope */ } /* End PCI0 scope */