mb/intel/shadowmountain: Update mainboard properties

This changes updates mainboard properties by adding DFP number and
power_gpio for each DFP.

BUG=b:186521258
TEST=None

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I29480bf77f7df9890bef64a5f9f02074a34dc131
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
John Zhao 2021-05-13 23:08:16 -07:00 committed by Tim Wawrzynczak
parent d4717cf3a4
commit 7e982b1dd9
1 changed files with 8 additions and 1 deletions

View File

@ -188,7 +188,14 @@ chip soc/intel/alderlake
device pci 0a.0 off end # Crash-log SRAM
device pci 0d.0 on end # USB xHCI
device pci 0d.1 off end # USB xDCI (OTG)
device pci 0d.2 on end # TBT DMA0
device pci 0d.2 on
chip drivers/intel/usb4/retimer
register "dfp" = "{
[0] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H19),},
[1] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H19),}}"
device generic 0 on end
end
end
device pci 0d.3 on end # TBT DMA1
device pci 0e.0 off end # VMD
device pci 10.0 off end