soc/intel/skylake: Add support for all UART port index

Select LPSS UART Base address based on LPSS UART port index.

Change-Id: I306d3d299f8d6a890ae519c74008f9d0d9dd1a76
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/skylake/include/soc/iomap.h

@@ -23,8 +23,11 @@
 #define MCFG_BASE_ADDRESS	CONFIG_MMCONF_BASE_ADDRESS
 #define MCFG_BASE_SIZE		0x4000000
 
-#define UART_DEBUG_BASE_ADDRESS	0xfe034000
+#define UART_DEBUG_BASE_0_SIZE	0x1000
-#define UART_DEBUG_BASE_SIZE	0x1000
+#define UART_BASE_0_ADDRESS	0xfe030000
+/* Both UART BAR 0 and 1 are 4KB in size */
+#define UART_BASE_0_ADDR(x)	(UART_BASE_0_ADDRESS + (2 * \
+					UART_DEBUG_BASE_0_SIZE * (x)))
 
 #define EARLY_I2C_BASE_ADDRESS	0xfe040000
 #define EARLY_I2C_BASE(x)	(EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))

src/soc/intel/skylake/uart.c

@@ -30,8 +30,8 @@ void pch_uart_read_resources(struct device *dev)
 	if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) {
 		struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
 		/* Need to set the base and size for the resource allocator. */
-		res->base = UART_DEBUG_BASE_ADDRESS;
+		res->base = UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE);
-		res->size = UART_DEBUG_BASE_SIZE;
+		res->size = UART_DEBUG_BASE_0_SIZE;
 		res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
 			IORESOURCE_FIXED;
 	}

src/soc/intel/skylake/uart_debug.c

@@ -22,5 +22,5 @@ uintptr_t uart_platform_base(int idx)
 {
 	/* Same base address for all debug port usage. In reality UART2
 	 * is currently only supported. */
-	return UART_DEBUG_BASE_ADDRESS;
+	return UART_BASE_0_ADDR(idx);
 }