Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26

Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/370
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

src/northbridge/amd/amdk8/raminit_f.c

@@ -1446,7 +1446,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i
 		18,	/* *Supported CAS Latencies */
 		9,	/* *Cycle time at highest CAS Latency CL=X */
 		23,	/* *Cycle time at CAS Latency (CLX - 1) */
-		26,	/* *Cycle time at CAS Latency (CLX - 2) */
+		25,	/* *Cycle time at CAS Latency (CLX - 2) */
 	};
 	u32 dcl, dcm;
 	u8 common_cl;