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device/dram/ddr2.c: Decoding byte[12] bit7 as self refresh flag 

"Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3)" note
4 says bit7 of byte 12 indicates whether the assembly supports self
refresh.

This patch decodes this and modifies decoding tRR accordingly.

Change-Id: I091121a5d08159cea4befdedb5f3a92ce132c6e5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Arthur Heymans 2017-09-21 08:28:23 +02:00 committed by Nico Huber
parent c88e370f85
commit 7eb0157fca
2 changed files with 12 additions and 7 deletions
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17
src/device/dram/ddr2.c
View File

@ -188,26 +188,26 @@ static u32 spd_decode_quarter_time(u8 c)
*/
static int spd_decode_tRR_time(u32 *tRR, u8 c)
{
switch (c) {
switch (c & ~0x80) {
default:
printk(BIOS_WARNING, "Invalid tRR value 0x%x\n", c);
return CB_ERR;
case 0x80:
case 0x0:
*tRR = 15625 << 8;
break;
case 0x81:
case 0x1:
*tRR = 15625 << 6;
break;
case 0x82:
case 0x2:
*tRR = 15625 << 7;
break;
case 0x83:
case 0x3:
*tRR = 15625 << 9;
break;
case 0x84:
case 0x4:
*tRR = 15625 << 10;
break;
case 0x85:
case 0x5:
*tRR = 15625 << 11;
break;
}
@ -545,6 +545,9 @@ int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
/* Refresh rate in us */
if (spd_decode_tRR_time(&dimm->tRR, spd[12]) != CB_SUCCESS)
ret = SPD_STATUS_INVALID_FIELD;
dimm->flags.self_refresh = (spd[12] >> 7) & 1;
printram("The assembly supports self refresh: %s\n",
dimm->flags.self_refresh ? "true", "false");
/* Number of PLLs on DIMM */
if (dimm->rev >= 0x11)

2
src/include/device/dram/ddr2.h
View File

@ -119,6 +119,8 @@ union dimm_flags_st {
unsigned bl4:1;
/* DIMM Package is stack */
unsigned stacked:1;
/* the assembly supports self refresh */
unsigned self_refresh:1;
};
unsigned int raw;
};