device/dram/ddr2.c: Decoding byte[12] bit7 as self refresh flag
"Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3)" note 4 says bit7 of byte 12 indicates whether the assembly supports self refresh. This patch decodes this and modifies decoding tRR accordingly. Change-Id: I091121a5d08159cea4befdedb5f3a92ce132c6e5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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@ -188,26 +188,26 @@ static u32 spd_decode_quarter_time(u8 c)
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*/
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static int spd_decode_tRR_time(u32 *tRR, u8 c)
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{
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switch (c) {
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switch (c & ~0x80) {
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default:
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printk(BIOS_WARNING, "Invalid tRR value 0x%x\n", c);
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return CB_ERR;
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case 0x80:
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case 0x0:
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*tRR = 15625 << 8;
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break;
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case 0x81:
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case 0x1:
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*tRR = 15625 << 6;
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break;
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case 0x82:
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case 0x2:
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*tRR = 15625 << 7;
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break;
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case 0x83:
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case 0x3:
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*tRR = 15625 << 9;
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break;
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case 0x84:
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case 0x4:
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*tRR = 15625 << 10;
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break;
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case 0x85:
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case 0x5:
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*tRR = 15625 << 11;
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break;
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}
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@ -545,6 +545,9 @@ int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
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/* Refresh rate in us */
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if (spd_decode_tRR_time(&dimm->tRR, spd[12]) != CB_SUCCESS)
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ret = SPD_STATUS_INVALID_FIELD;
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dimm->flags.self_refresh = (spd[12] >> 7) & 1;
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printram("The assembly supports self refresh: %s\n",
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dimm->flags.self_refresh ? "true", "false");
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/* Number of PLLs on DIMM */
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if (dimm->rev >= 0x11)
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@ -119,6 +119,8 @@ union dimm_flags_st {
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unsigned bl4:1;
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/* DIMM Package is stack */
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unsigned stacked:1;
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/* the assembly supports self refresh */
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unsigned self_refresh:1;
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};
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unsigned int raw;
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};
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