updates for the E325

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1460 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2004-03-22 04:23:57 +00:00
parent 132f2c4900
commit 7ebb9e9eb8
4 changed files with 17 additions and 13 deletions

View File

@ -82,7 +82,7 @@ int console_tst_byte(void)
*/
void post_code(uint8_t value)
{
#if !defined(NO_POST)
#if NO_POST==0
#if CONFIG_SERIAL_POST==1
printk_emerg("POST: 0x%02x\n", value);
#endif

View File

@ -161,7 +161,7 @@ static void main(void)
#endif
};
int needs_reset;
print_emerg("H\n");
enable_lapic();
init_timer();
if (cpu_init_detected()) {
@ -181,7 +181,7 @@ static void main(void)
print_info("ht reset -");
soft_reset();
}
print_emerg("HER\n");
#if 0
print_pci_devices();
#endif
@ -199,10 +199,10 @@ static void main(void)
dump_pci_device(PCI_DEV(0, 0x18, 2));
#endif
print_err("LET'S DO SOME MEMORY\n");
#if 1
/* Check the first 1M */
ram_check(0x00000000, 0x000100000);
ram_check(0x00000000, 0x001000000);
#endif
}

View File

@ -93,13 +93,13 @@ void ram_check(unsigned long start, unsigned long stop)
* test than a "Is my DRAM faulty?" test. Not all bits
* are tested. -Tyson
*/
print_debug("Testing DRAM : ");
print_debug_hex32(start);
print_debug("-");
print_debug_hex32(stop);
print_debug("\r\n");
print_err("Testing DRAM : ");
print_err_hex32(start);
print_err("-");
print_err_hex32(stop);
print_err("\r\n");
ram_fill(start, stop);
ram_verify(start, stop);
print_debug("Done.\r\n");
print_err("Done.\r\n");
}

View File

@ -10,6 +10,8 @@ uses CONFIG_COMPRESS
uses CONFIG_IOAPIC
uses CONFIG_ROM_STREAM
uses CONFIG_ROM_STREAM_START
uses CONFIG_SERIAL_POST
uses NO_POST
uses CONFIG_UDELAY_TSC
uses CPU_FIXUP
uses FALLBACK_SIZE
@ -51,9 +53,11 @@ uses LINUXBIOS_EXTRA_VERSION
option CONFIG_CHIP_CONFIGURE=1
option MAXIMUM_CONSOLE_LOGLEVEL=8
option DEFAULT_CONSOLE_LOGLEVEL=8
option MAXIMUM_CONSOLE_LOGLEVEL=9
option DEFAULT_CONSOLE_LOGLEVEL=9
option CONFIG_CONSOLE_SERIAL8250=1
option CONFIG_SERIAL_POST=1
option NO_POST=0
option CPU_FIXUP=1
option CONFIG_UDELAY_TSC=0