AMD S3: Add a document about S3 on AMD platform
See the document. Need review. Everything should be in Authentic English. Change-Id: Idc528b8c6b0d5afe08fc4f4387b7bff30698f677 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1400 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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_____ ____ _____ ______ ____ ____ ____ _______
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/ ____/ __ \| __ \| ____| _ \ / __ \ / __ \__ __|
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| | | | | | |__) | |__ | |_) | | | | | | | | |
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| | | | | | _ /| __| | _ <| | | | | | | | |
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| |___| |__| | | \ \| |____| |_) | |__| | |__| | | |
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\_____\____/|_| \_\______|____/ \____/ \____/ |_|
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__ __ _____ _____ ____
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/\ | \/ | __ \ / ____| |___ \
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/ \ | \ / | | | | | (___ __) |
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/ /\ \ | |\/| | | | | \___ \ |__ <
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/ ____ \| | | | |__| | ____) | ___) |
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/_/ \_\_| |_|_____/ |_____/ |____/
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S3 in Coreboot (V 1.1)
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----------------------------------------
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Zheng Bao
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<zheng.bao@amd.com>
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<fishbaozi@gmail.com>
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Introduction
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============
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This document is about how the feature S3 is implemented on coreboot,
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specificly on AMD platform. This topic deals with ACPI spec, hardware,
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BIOS, OS. We try to help coreboot users to realize their own S3.
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S3 in a nutshell
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================
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The S3 sleeping state is a low wake latency sleeping state where all
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system context is lost except system memory. [1]. S3 is a ACPI
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definition.
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To enter S3, write 3 in SLP_TYPx and set the SLP_EN bit (See ACPI
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registers). But if you do that, board can not resume at where it
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sleeps, because you don't save the context. More often than not, we
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make the board go into S3 by the tools which OSes provide. For
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windows, click Start->sleep. For linux, some distribution provide a
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tools called pm-suspend, which can make the system goto S3. If
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pm-suspend is not available, we can run "echo mem > /sys/power/state",
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but this way may not save all the needed context.
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In S3 state, the power is off. So when the power button is pressed,
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BIOS runs as it does in cold boot. If BIOS didn't detect whether
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board boots or resumes, it would go the same way as boot. It is not
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what we expect. BIOS detects the SLP_TYPx. If it is 3, it means BIOS
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are waking up.
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BIOS is responsible for restore the machine state as it is before
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sleep. It needs restore the memory controller, not overwriting memory
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which is not marked as reserved. For the peripheral which loses its
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registers, BIOS needs to write the original value.
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When everything is done, BIOS needs to find out the wakeup vector
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provided by OSes and jump there. OSes also have work to do. We can go
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to linux kernel or some other open source projects to find out how they
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handle S3 resume.
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ACPI registers
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==============
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ACPI specification defines a group of registers. OSes handle all these
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registers to read and write status to all the platform.
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On AMD platform, these registers are provided by southbridge. For
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example, Hudson uses PMIO 60:6F to define ACPI registers.
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OSes don't have any specific driver to know where these registers
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are. BIOS has the responsibility to allocated the IO resources and
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write all these address to FADT, a ACPI defined table.
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Memory Layout
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=============
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Restoring memory is the most important job done by BIOS. When the
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power is off, the memory is maintained by standby power. BIOS need to
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make sure that when flow goes to OS, everything in memory should be
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the same as it was.
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The chip vendor will provide a way, or code, to wake up the memory
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from sleeping. In AGESA 2008 arch, it is called AmdInitResume.
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The BIOS itself needs some memory to run. Either, BIOS marks the erea
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as reserved in e820, or BIOS saves the content into reserved space.
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Here is the address Map for S3 Resume. Assumingly the total memory is 1GB.
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00000000 --- 00100000 BIOS Reserved area.
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00100000 --- 00200000 Free
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00200000 --- 01000000 Coreboot ramstage area.
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01000000 --- 2e160000 Free
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2e160000 --- 2e170000 ACPI table
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2e170000 --- 2ef70000 OSRAM
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2ef70000 --- 2efe0000 Stack in highmem
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2efe0000 --- 2f000000 heap in highmem
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2f000000 TOM
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AMD requirements in S3
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======================
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Chip vendor like AMD will provide bunch of routines to restore the
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board.[2]
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* AmdS3Save: It is called in cold boot, save required register into
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non-volatile storage. Currently, we use SPI flash to store the data.
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* AmdInitResume: Restore the memory controller.
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* AmdS3LateRestore: Called after AmdInitResume, restore other
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register that memory.
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* (SouthBridge)InitS3EarlyRestore, (SouthBridge)InitS3LateRestore:
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Provided by Southbridge vendor code. Early is called before PCI
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enumeration, and Late is called after that.
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Lifecycle of booting, sleeping and waking Coreboot and Ubuntu
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=============================================================
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1. Cold boot.
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For a system with S3 feature, the BIOS needs to save some data to
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non-volitile storage at cold boot stage. What data need to be save are
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provided by AmdS3Save. After the wrapper calls the AmdS3Save, it gets
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the VolatileStorage and NvStorage, which are where the data are
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located. It is the wrappers's responsibility to save the data.[3][4]
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Currently, the wrappers allocate a CBFS modules in BIOS image. Todo
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that, the wrapper needs to have the ability to write flash chips. It
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is not as comprehensive as flashrom. But for the SST chip on Parmer,
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MX chip on Thather, coreboot works well.[5]
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2. OS goes in S3.
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3. BIOS detect S3 wakeup
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4. OS resumes.
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Reference
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=========
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[1] ACPI40a, http://www.acpi.info/spec40a.htm
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[2] Coreboot Vendorcode, {top}/src/vendorcode/amd/agesa/{family}/Proc/Common/
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[3] Coreboot AGESA wrapper, {top}/src/mainboard/amd/parmer/agesawrapper.c
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[4] Coreboot AGESA wrapper, {top}/src/cpu/amd/agesa/s3_resume.c
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[5] Coreboot Southbridge, {top}/src/southbridge/amd/agesa/hudson/spi.c
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