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mainboard/google/kahlee: Update PCIe port map 

- Grunt moved the EMMC chip to port 2, where Kahlee had the SD reader on
PCIe port 1, so move the OemCustomize file into the variant directory.
- Add comments in baseboard version so it's easier to understand.
- Update reset pins, put the definitions in gpio.h

BUG=b:70255003
TEST=Build and boot Kahlee.  Build Grunt.

Change-Id: I78ec72e9d6fd52b8ac75e7187bd01ee7ddc3ba2a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This commit is contained in:
Martin Roth 2017-12-06 01:03:47 -07:00
parent 9e0dd0169d
commit 7eda534ad5
7 changed files with 171 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/kahlee/Makefile.inc
View File

@ -15,7 +15,6 @@
bootblock-y += bootblock/bootblock.c
bootblock-y += BiosCallOuts.c
bootblock-y += bootblock/OemCustomize.c
bootblock-y += ec.c
romstage-y += BiosCallOuts.c

1
src/mainboard/google/kahlee/variants/baseboard/Makefile.inc
View File

@ -14,6 +14,7 @@
#
bootblock-y += gpio.c
bootblock-y += OemCustomize.c
romstage-y += gpio.c
romstage-y += memory.c

151
src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c Normal file
View File

@ -0,0 +1,151 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <agesawrapper.h>
#include <variant/gpio.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER_V2(
PortDisabled, /* mPortPresent */
ChannelTypeExt6db, /* mChannelType */
2, /* mDevAddress */
1, /* mDevFunction */
HotplugDisabled, /* mHotplug */
PcieGenMaxSupported, /* mMaxLinkSpeed */
PcieGenMaxSupported, /* mMaxLinkCap */
AspmL0sL1, /* mAspm */
0, /* mResetId */
0) /* mClkPmSupport */
},
/* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
PCIE_PORT_DATA_INITIALIZER_V2(
PortEnabled, /* mPortPresent */
ChannelTypeExt6db, /* mChannelType */
2, /* mDevAddress */
2, /* mDevFunction */
HotplugDisabled, /* mHotplug */
PcieGenMaxSupported, /* mMaxLinkSpeed */
PcieGenMaxSupported, /* mMaxLinkCap */
AspmL0sL1, /* mAspm */
PCIE_0_RST, /* mResetId */
0) /* mClkPmSupport */
},
/* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) NC */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
PCIE_PORT_DATA_INITIALIZER_V2(
PortDisabled, /* mPortPresent */
ChannelTypeExt6db, /* mChannelType */
2, /* mDevAddress */
3, /* mDevFunction */
HotplugDisabled, /* mHotplug */
PcieGenMaxSupported, /* mMaxLinkSpeed */
PcieGenMaxSupported, /* mMaxLinkCap */
AspmL0sL1, /* mAspm */
PCIE_1_RST, /* mResetId */
0) /* mClkPmSupport */
},
/* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for EMMC */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 2, 2),
PCIE_PORT_DATA_INITIALIZER_V2(
PortEnabled, /* mPortPresent */
ChannelTypeExt6db, /* mChannelType */
2, /* mDevAddress */
4, /* mDevFunction */
HotplugDisabled, /* mHotplug */
PcieGenMaxSupported, /* mMaxLinkSpeed */
PcieGenMaxSupported, /* mMaxLinkCap */
AspmL0sL1, /* mAspm */
PCIE_2_RST, /* mResetId */
0) /* mClkPmSupport */
},
/* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 3, 3),
PCIE_PORT_DATA_INITIALIZER_V2(
PortDisabled, /* mPortPresent */
ChannelTypeExt6db, /* mChannelType */
2, /* mDevAddress */
5, /* mDevFunction */
HotplugDisabled, /* mHotplug */
PcieGenMaxSupported, /* mMaxLinkSpeed */
PcieGenMaxSupported, /* mMaxLinkCap */
AspmL0sL1, /* mAspm */
PCIE_3_RST, /* mResetId */
0) /* mClkPmSupport */
},
};
static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* DDI0 - eDP */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)
},
/* DDI1 - DP */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
},
/* DDI2 - DP */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
},
};
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
.Flags = DESCRIPTOR_TERMINATE_LIST,
.SocketId = 0,
.PciePortList = (void *)PortList,
.DdiLinkList = (void *)DdiList
};
/*---------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This is the stub function will call the host environment through the
* binary block interface (call-out port) to provide a user hook opportunity.
*
* Parameters:
* @param[in] **PeiServices
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------*/
VOID __attribute__((weak)) OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
{
InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;
InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;
InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;
}

6
src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
View File

@ -28,6 +28,12 @@
#define CROS_WP_GPIO GPIO_122
#define GPIO_EC_IN_RW GPIO_15
/* PCIe reset pins */
#define PCIE_0_RST GPIO_70
#define PCIE_1_RST 0
#define PCIE_2_RST GPIO_40
#define PCIE_3_RST 0
#endif /* _ACPI__ */
#define EC_SCI_GPI 22

1
src/mainboard/google/kahlee/variants/kahlee/Makefile.inc
View File

@ -14,6 +14,7 @@
#
bootblock-y += gpio.c
bootblock-y += OemCustomize.c
romstage-y += gpio.c
romstage-y += memory.c

11
src/mainboard/google/kahlee/bootblock/OemCustomize.c → src/mainboard/google/kahlee/variants/kahlee/OemCustomize.c
View File

@ -14,6 +14,7 @@
*/
#include <agesawrapper.h>
#include <variant/gpio.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/
@ -25,7 +26,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmL0sL1, 0x04, 0)
AspmL0sL1, 0, 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */
{
@ -36,7 +37,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmL0sL1, 0x2, 0)
AspmL0sL1, PCIE_0_RST, 0)
},
/* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) for Card Reader */
{
@ -47,7 +48,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmL0sL1, 0x3, 0)
AspmL0sL1, PCIE_1_RST, 0)
},
/* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for NC */
{
@ -58,7 +59,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmL0sL1, 0, 0)
AspmL0sL1, PCIE_2_RST, 0)
},
/* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */
{
@ -69,7 +70,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmL0sL1, 0, 0)
AspmL0sL1, PCIE_3_RST, 0)
},
};

6
src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h
View File

@ -32,6 +32,12 @@
#define CROS_WP_GPIO GPIO_142
#define GPIO_EC_IN_RW GPIO_15
/* PCIe reset pins */
#define PCIE_0_RST GPIO_119
#define PCIE_1_RST 0
#define PCIE_2_RST 0
#define PCIE_3_RST 0
#endif /* _ACPI__ */
/* AGPIO22 -> GPE3 */