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nb/intel/pineview: Correct HICLKGTCTL write 

Reference code uses the `0x06` as an or-mask, which makes more sense.

Change-Id: I04e5262d9ab36ae866fccd90255e4a0f85328e85
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51859
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-03-26 18:33:31 +01:00 committed by Nico Huber
parent 7383318856
commit 7ee1c47cba
1 changed files with 1 additions and 1 deletions
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src/northbridge/intel/pineview/raminit.c
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@ -2320,7 +2320,7 @@ static void sdram_powersettings(struct sysinfo *s)
MCHBAR8_AND(CISDCTRL + 3, ~0x80); MCHBAR8_AND(CISDCTRL + 3, ~0x80);
MCHBAR16_AND(CICGDIS, ~0x1fff); MCHBAR16_AND(CICGDIS, ~0x1fff);
MCHBAR32_AND(SBCLKGATECTRL, ~0x0001ffff); MCHBAR32_AND(SBCLKGATECTRL, ~0x0001ffff);
MCHBAR16_AND(HICLKGTCTL, ~0x03ff & 0x06); MCHBAR16_AND_OR(HICLKGTCTL, ~0x03ff, 0x06);
MCHBAR32_AND_OR(HTCLKGTCTL, ~0xffffffff, 0x20); MCHBAR32_AND_OR(HTCLKGTCTL, ~0xffffffff, 0x20);
MCHBAR8_AND(TSMISC, ~1); MCHBAR8_AND(TSMISC, ~1);
MCHBAR8(C0WRDPYN) = s->selected_timings.CAS - 1 + 0x15; MCHBAR8(C0WRDPYN) = s->selected_timings.CAS - 1 + 0x15;