diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c
index 05ac8c6dd3..c8af85807e 100644
--- a/src/mainboard/amd/parmer/buildOpts.c
+++ b/src/mainboard/amd/parmer/buildOpts.c
@@ -194,24 +194,6 @@
 // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
 // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
 
-CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
-{
-  { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
-  { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
-  { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
-  { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
-  { CPU_LIST_TERMINAL }
-};
-
-#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
-
 /* Include the files that instantiate the configuration definitions. */
 #include "cpuRegisters.h"
 #include "cpuFamRegisters.h"
diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c
index a97e8f0952..c4e0fce9a9 100644
--- a/src/mainboard/amd/thatcher/buildOpts.c
+++ b/src/mainboard/amd/thatcher/buildOpts.c
@@ -194,24 +194,6 @@
 // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
 // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
 
-CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
-{
-  { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
-  { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
-  { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
-  { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
-  { CPU_LIST_TERMINAL }
-};
-
-#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
-
 /* Include the files that instantiate the configuration definitions. */
 #include "cpuRegisters.h"
 #include "cpuFamRegisters.h"
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
index 8bb0b80cf4..13f2bd80af 100644
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m/buildOpts.c
@@ -207,24 +207,6 @@
 // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
 // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
 
-CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
-{
-  { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
-  { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
-  { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
-  { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
-  { CPU_LIST_TERMINAL }
-};
-
-#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
-
 /* MEMORY_BUS_SPEED */
 #define DDR400_FREQUENCY   200     ///< DDR 400
 #define DDR533_FREQUENCY   266     ///< DDR 533
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
index 8e90a08ebf..19aac23fdd 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
@@ -208,24 +208,6 @@
 // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
 // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
 
-CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
-{
-  { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
-  { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
-  { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
-  { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
-  { CPU_LIST_TERMINAL }
-};
-
-#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
-
 /* MEMORY_BUS_SPEED */
 #define DDR400_FREQUENCY   200     ///< DDR 400
 #define DDR533_FREQUENCY   266     ///< DDR 533
diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c
index fd1c977da4..92a1c6921b 100644
--- a/src/mainboard/lenovo/g505s/buildOpts.c
+++ b/src/mainboard/lenovo/g505s/buildOpts.c
@@ -208,24 +208,6 @@
 // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
 // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
 
-CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
-{
-  { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
-  { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
-  { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
-  { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
-  { CPU_LIST_TERMINAL }
-};
-
-#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
-
 /* MEMORY_BUS_SPEED */
 #define DDR400_FREQUENCY   200     ///< DDR 400
 #define DDR533_FREQUENCY   266     ///< DDR 533
diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c
index c969d54d5e..c7c44267f6 100644
--- a/src/mainboard/msi/ms7721/buildOpts.c
+++ b/src/mainboard/msi/ms7721/buildOpts.c
@@ -207,24 +207,6 @@
 // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
 // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
 
-CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
-{
-  { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
-  { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
-  { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
-  { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
-  { CPU_LIST_TERMINAL }
-};
-
-#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
-
 /* MEMORY_BUS_SPEED */
 #define DDR400_FREQUENCY   200     ///< DDR 400
 #define DDR533_FREQUENCY   266     ///< DDR 533
diff --git a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h
index d769220dd2..1bca388000 100644
--- a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h
@@ -62,6 +62,22 @@ VOLATILE  AMD_MODULE_HEADER mCpuModuleID = {
   NULL
 };
 
+/* The default fixed MTRR values to be set after memory initialization */
+static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
+{
+	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
+	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
+	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
+	{ AMD_AP_MTRR_FIX4k_C0000,  0x0000000000000000 },
+	{ AMD_AP_MTRR_FIX4k_C8000,  0x0000000000000000 },
+	{ AMD_AP_MTRR_FIX4k_D0000,  0x0000000000000000 },
+	{ AMD_AP_MTRR_FIX4k_D8000,  0x0000000000000000 },
+	{ AMD_AP_MTRR_FIX4k_E0000,  0x1818181818181818 },
+	{ AMD_AP_MTRR_FIX4k_E8000,  0x1818181818181818 },
+	{ AMD_AP_MTRR_FIX4k_F0000,  0x1818181818181818 },
+	{ AMD_AP_MTRR_FIX4k_F8000,  0x1818181818181818 },
+	{ CPU_LIST_TERMINAL },
+};
 
 /* Process solution defined socket / family installations
  *
@@ -2425,7 +2441,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
   #define CFG_AP_MTRR_SETTINGS_LIST           (BLDCFG_AP_MTRR_SETTINGS_LIST)
 #else
-  #define CFG_AP_MTRR_SETTINGS_LIST           (NULL)
+  #define CFG_AP_MTRR_SETTINGS_LIST           (TrinityApMtrrSettingsList)
 #endif
 
 #ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST