From 7f00965209c0c48a6e060d435d07f463f869d532 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Wed, 13 Sep 2017 18:41:05 -0700
Subject: [PATCH] mainboard/intel/cannonlake_rvp: Add PCI, PCIE IRQs to DSDT
 table

Change-Id: Id0b2b9e9ae2755ed89cee337a1a085fc4e95b073
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/mainboard/intel/cannonlake_rvp/dsdt.asl | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
index 712ea0524a..9f19cfb3ac 100644
--- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl
+++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
@@ -28,6 +28,11 @@ DefinitionBlock(
 	#include <soc/intel/cannonlake/acpi/globalnvs.asl>
 
 	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/cannonlake/acpi/northbridge.asl>
+			#include <soc/intel/cannonlake/acpi/southbridge.asl>
+		}
 	}
 
 	#if IS_ENABLED(CONFIG_CHROMEOS)