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nb/intel/sandybridge: Program MR2 shadow register 

This register must be programmed if Self-Refresh Temperature range is
enabled in MR2 (bit 7). Because the memory controller needs to reprogram
MR2 when entering Self-Refresh, it needs a copy of the MR2 settings. It
also needs to know about mirrored ranks to correctly issue MRS commands.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: I2e459ac7907ead75826c7d2ded42328286eb9377
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-11-13 13:31:58 +01:00
parent f999748fb3
commit 7f1363d9b4
1 changed files with 16 additions and 0 deletions
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16
src/northbridge/intel/sandybridge/raminit_common.c
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@ -775,6 +775,22 @@ static void dram_mr2(ramctr_timing *ctrl, u8 rank, int channel)
mr2reg |= (odt.rttwr / 60) << 9;
write_mrreg(ctrl, channel, rank, 2, mr2reg);
/* Program MR2 shadow */
u32 reg32 = MCHBAR32(TC_MR2_SHADOW_ch(channel));
reg32 &= 3 << 14 | 3 << 6;
reg32 |= mr2reg & ~(3 << 6);
if (rank & 1) {
if (srt)
reg32 |= 1 << (rank / 2 + 6);
} else {
if (ctrl->rank_mirror[channel][rank])
reg32 |= 1 << (rank / 2 + 14);
}
MCHBAR32(TC_MR2_SHADOW_ch(channel)) = reg32;
}
static void dram_mr3(ramctr_timing *ctrl, u8 rank, int channel)