From 7f149c7bb4744459c775c32c71fe222c792cea19 Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Thu, 7 Jul 2016 14:48:21 -0700 Subject: [PATCH] soc/intel/apollolake: Add handler for SCI This patch adds the handler to enable bit for gpio_tier1_sci_en. gpio_tier1_sci_en enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event and/or an SCI or SMI#. We are setting the bit for gpio_tier1_sci_en from the ASL code as OS clears this bit if set from BIOS. As per ACPI spec _GPE is defined as the Named Object that evaluates to either an integer or a package. If _GPE evaluates to an integer, the value is the bit assignment of the SCI interrupt within the GPEx_STS register of a GPE block described in the FADT that the embedded controller will trigger. FADT right now has no mechanism to acheive the same. Change-Id: I1e1bd3f5c89a5e6bea2d1858569a9d30e6da78fe Signed-off-by: Shaunak Saha Reviewed-on: https://review.coreboot.org/15578 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/acpi/gpio.asl | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl index 4bf04428eb..f2a7e76f20 100644 --- a/src/soc/intel/apollolake/acpi/gpio.asl +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -142,3 +142,13 @@ scope (\_SB) { } } } + +Scope(\_GPE) +{ + /* Dummy method for the Tier 1 GPIO SCI enable bit. When kernel reads + * _L0F in scope GPE it sets bit for gpio_tier1_sci_en in acpi enable + * register at 0x430. For APL acpi enable register DW0 i.e., ACPI + * GPE0a_EN at 0x430 is reserved. + */ + Method(_L0F, 0) {} +}