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Intel Sandybridge and UMA: use mmio_resource() 

With SandyBridge northbridge code, uma_memory_size was reset to
zero before variable MTRRs were set. This means MTRR setup routine
did not previously create a un-cacheable hole for uma.

Keep the behaviour that way, mmio_resource() has a prerequisuite that
the new region does not overlap with any cacheable ram_resource().

The result is not optimal setup in the number of used MTRRs, but
continue with this approach until MTRR algorithm is improved.

Change-Id: I63c8df19ad6b6350d46a3eca3055abf684b8b114
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1373
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
This commit is contained in:
Kyösti Mälkki 2012-07-27 13:12:03 +03:00 committed by Anton Kochkov
parent 1ec5e744c6
commit 7f189cc74e
1 changed files with 12 additions and 11 deletions
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23
src/northbridge/intel/sandybridge/northbridge.c
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@ -111,17 +111,18 @@ static void add_fixed_resources(struct device *dev, int index)
struct resource *resource; struct resource *resource;
u32 pcie_config_base, pcie_config_size; u32 pcie_config_base, pcie_config_size;
printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx " /* Using uma_resource() here would fail as base & size cannot
"size=0x%llx\n", uma_memory_base, uma_memory_size); * be used as-is for a single MTRR. This would cause excessive
resource = new_resource(dev, index++); * use of MTRRs.
resource->base = (resource_t) uma_memory_base; *
resource->size = (resource_t) uma_memory_size; * Use of mmio_resource() instead does not create UC holes by using
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | * MTRRs, but making these regions uncacheable is taken care of by
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; * making sure they do not overlap with any ram_resource().
*
/* Clear these values here so they don't get used by MTRR code */ * The resources can be changed to use separate mmio_resource()
uma_memory_base = 0; * calls after MTRR code is able to merge them wisely.
uma_memory_size = 0; */
mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "