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Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML" 

This reverts commit 41dad286d8. The change will make s0ix fail on Sarien/Arcada Platform.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I169bc6f41fba82fcf515267e8e1d08aa5ee2dce4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32391
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao 2019-04-22 21:17:58 +00:00 committed by Duncan Laurie
parent 69eae2762f
commit 7f1a0e6b4c
3 changed files with 1 additions and 17 deletions
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8
src/soc/intel/cannonlake/Kconfig
View File

@ -27,8 +27,6 @@ config SOC_INTEL_WHISKEYLAKE
bool bool
default n default n
select SOC_INTEL_COMMON_CANNONLAKE_BASE select SOC_INTEL_COMMON_CANNONLAKE_BASE
select FSP_PEIM_TO_PEIM_INTERFACE
select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
help help
Intel Whiskeylake support Intel Whiskeylake support
@ -36,12 +34,6 @@ config SOC_INTEL_COMETLAKE
bool bool
default n default n
select SOC_INTEL_COMMON_CANNONLAKE_BASE select SOC_INTEL_COMMON_CANNONLAKE_BASE
# TODO:
# Delete FSP_PEIM_TO_PEIM_INTERFACE and
# USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI selection
# and select PLATFORM_USES_FSP2_1 once FSP support for CML is ready
select FSP_PEIM_TO_PEIM_INTERFACE
select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
help help
Intel Cometlake support Intel Cometlake support

5
src/soc/intel/cannonlake/fsp_params.c
View File

@ -18,9 +18,7 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <fsp/api.h> #include <fsp/api.h>
#include <fsp/ppi/mp_service_ppi.h>
#include <fsp/util.h> #include <fsp/util.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/xdci.h> #include <intelblocks/xdci.h>
#include <soc/intel/common/vbt.h> #include <soc/intel/common/vbt.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
@ -144,9 +142,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Usb3OverCurrentPin[i] = 0; params->Usb3OverCurrentPin[i] = 0;
} }
if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
mainboard_silicon_init_params(params); mainboard_silicon_init_params(params);
/* Set PsysPmax if it is available from DT */ /* Set PsysPmax if it is available from DT */

3
src/soc/intel/cannonlake/romstage/fsp_params.c
View File

@ -65,9 +65,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
m_cfg->VmxEnable = CONFIG(ENABLE_VMX); m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
#if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) #if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE)
if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
m_cfg->SkipMpInit = 0;
else
m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
#endif #endif