AMD Thatcher: Fix PCIE link issues
1). Thatcher PCIE x8 slot is reverse order. Although the PCIE slot is x16, it actually uses 8 lanes(15:8). Because the PCIE slot is configured by PortList[0], fix this item can enable the slot. A x1 PCIE network adapter works well in this slot. 2). Fix DdiList to detect DP monitor or HDMI monitor. GPIO50 can be used to detect DP0/HDMI0 monitor. If GPIO50 is 1, it is DP monitor. If GPIO50 is 0, it is HDMI monitor. GPIO51 can be used to detect DP1/HDMI1 in the same way. 3). Disable unused PCIE port and clean up code in PlatformGnbPcie.c and devicetree.cb. PCIE port 3 and 7 are not used in Thatcher. Change-Id: I8524b6fc1b6cdc03ba92e7191186bfb0986767c8 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3011 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
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@ -23,100 +23,79 @@
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#include "heapManager.h"
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#include "PlatformGnbPcieComplex.h"
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#include "Filecode.h"
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#include "Fch.h"
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#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
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PCIe_PORT_DESCRIPTOR PortList [] = {
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/* PCIe port, Lanes 8:23, PCI Device Number 2 */
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/* PCIe port, Lanes 15:8, PCI Device Number 2, PCIE SLOT x8 */
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{
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0, /* Descriptor flags */
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23),
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 15, 8),
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PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
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},
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/* PCIe port, Lanes 16:23, PCI Device Number 3 */
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/* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
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{
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0, /* Descriptor flags */
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PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23),
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PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
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},
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/* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */
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/* PCIe port, Lanes 4, PCI Device Number 4, LAN */
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{
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0, /* Descriptor flags */
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
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PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
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},
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/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */
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/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI0 */
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{
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0, /* Descriptor flags */
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
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PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
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},
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/* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1, TODO: Disabled. */
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/* PCIe port, Lanes 6, PCI Device Number 6, PCIE MINI1 */
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{
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0, /* Descriptor flags */
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
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PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
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},
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/* PCIe port, Lanes 7, PCI Device Number 7, LAN , TODO: not the last entry.*/
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/* PCIe port, Lanes 7, PCI Device Number 7, Disabled */
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{
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0, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */
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0, /* Descriptor flags */
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
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PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
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PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
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},
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#if 1
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/* Initialize Port descriptor (PCIe port, Lanes ?, PCI Device Number 8, ...) */
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/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
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{
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DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
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PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
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},
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#endif
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};
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PCIe_DDI_DESCRIPTOR DdiList [] = {
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// DP0 to HDMI0/DP
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// DP0 to HDMI0/DP0
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{
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0,
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1,
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1)
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
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},
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// DP1 to FCH
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// DP1 to HDMI1/DP1
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{
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0,
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1,
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
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},
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// DP2 to HDMI1/DP
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// DP2 to MINI-DDI Card
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{
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0,
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// PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 32, 38),
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1,
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35),
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//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3)
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3)
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3)
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},
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// GFX Lane 15-12
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 12, 15),
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux4, Hdp4)
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},
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// GFX Lane 11-8
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 19),
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux5, Hdp5)
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},
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// GFX Lane 7-4
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 20, 23),
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux6, Hdp6)
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}
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};
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PCIe_COMPLEX_DESCRIPTOR Trinity = {
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@ -151,6 +130,7 @@ OemCustomizeInitEarly (
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VOID *TrinityPcieComplexListPtr;
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VOID *TrinityPciePortPtr;
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VOID *TrinityPcieDdiPtr;
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UINT8 Value;
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ALLOCATE_HEAP_PARAMS AllocHeapParams;
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@ -161,7 +141,7 @@ OemCustomizeInitEarly (
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//
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AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) +
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sizeof (PCIe_PORT_DESCRIPTOR) * 7 +
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sizeof (PCIe_DDI_DESCRIPTOR)) * 6;
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sizeof (PCIe_DDI_DESCRIPTOR)) * 3;
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AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
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AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
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@ -192,12 +172,19 @@ OemCustomizeInitEarly (
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LibAmdMemFill (TrinityPcieDdiPtr,
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0,
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sizeof (PCIe_DDI_DESCRIPTOR) * 6,
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sizeof (PCIe_DDI_DESCRIPTOR) * 3,
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&InitEarly->StdHeader);
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LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader);
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LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader);
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LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader);
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LibAmdMemRead (AccessWidth8, ACPI_MMIO_BASE + GPIO_BASE + 50, &Value, &InitEarly->StdHeader);
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if (!(Value & 0x80))
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DdiList[0].Ddi.ConnectorType = ConnectorTypeHDMI;
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LibAmdMemRead (AccessWidth8, ACPI_MMIO_BASE + GPIO_BASE + 51, &Value, &InitEarly->StdHeader);
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if (!(Value & 0x80))
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DdiList[1].Ddi.ConnectorType = ConnectorTypeHDMI;
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LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 3, &InitEarly->StdHeader);
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((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr;
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((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
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@ -32,12 +32,12 @@ chip northbridge/amd/agesa/family15tn/root_complex
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device pci 0.0 on end # Root Complex
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device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
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device pci 1.1 on end # Internal Multimedia
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device pci 2.0 on end # PCIE SLOT0 x16
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device pci 3.0 on end # PCIE SLOT0 x16
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device pci 4.0 on end # PCIE MINI0
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device pci 5.0 on end # PCIE MINI1
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device pci 6.0 on end # PCIE Slot1 x1
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device pci 7.0 on end # LAN
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device pci 2.0 on end # PCIE SLOT0 x8
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device pci 3.0 off end
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device pci 4.0 on end # LAN
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device pci 5.0 on end # PCIE MINI0
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device pci 6.0 on end # PCIE MINI1
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device pci 7.0 off end
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device pci 8.0 off end # NB/SB Link P2P bridge
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end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
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