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mb/google/brya/acpi: Move dGPU power checks earlier 

Linux always "turns on" a PowerResource when it boots, regardless of
_STA, so the _ON routine should be idempotent. In this case, it all is,
except for the LTR restore, which would restore a value of 0 when _ON is
run the first time, which means that LTR is disabled on the root port
from then on, as the save/restore routines will keep saving/restoring
that 0. THis patch fixes the problem by moving the power checks from
PGON/PGOF to GCOO/GCOI.

BUG=b:244409563
TEST=boot agah and verify that LTR is still enabled on the root port

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4ed78323608eede5b8310598f1f1115497ab2b5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67278
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
This commit is contained in:
Tim Wawrzynczak 2022-09-01 11:48:38 -06:00 committed by Felix Held
parent d6ac209c74
commit 7f287d23bc
1 changed files with 12 additions and 13 deletions
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25
src/mainboard/google/brya/acpi/power.asl
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@ -182,12 +182,6 @@ Method (GC6O, 0, Serialized)
/* GCOFF exit sequence */
Method (PGON, 0, Serialized)
{
If (GPPS == GPU_POWER_STATE_ON)
{
Printf ("PGON: GPU already on")
Return
}
Local0 = Timer - GCOT
If (Local0 < MIN_OFF_TIME_TIMERS)
{
@ -234,12 +228,6 @@ Method (PGON, 0, Serialized)
/* GCOFF entry sequence */
Method (PGOF, 0, Serialized)
{
If (GPPS == GPU_POWER_STATE_OFF)
{
Printf ("GPU already off")
Return
}
/* Assert PERST# */
CTXS (GPIO_GPU_PERST_L)
@ -278,6 +266,12 @@ Method (PGOF, 0, Serialized)
/* GCOFF Out, i.e. full power-on sequence */
Method (GCOO, 0, Serialized)
{
If (GPPS == GPU_POWER_STATE_ON)
{
Printf ("PGON: GPU already on")
Return
}
SRCC (SRCCLK_ENABLE)
PGON ()
\_SB.PCI0.PEG0.LD23 ()
@ -310,9 +304,14 @@ Method (GCOO, 0, Serialized)
/* GCOFF In, i.e. full power-off sequence */
Method (GCOI, 0, Serialized)
{
If (GPPS == GPU_POWER_STATE_OFF)
{
Printf ("GPU already off")
Return
}
/* Save the PEG port's LTR setting */
SLTR = LREN
\_SB.PCI0.PEG0.DL23 ()
PGOF ()
SRCC (SRCCLK_DISABLE)