GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/*: Hook up device_operations in chipset.cb 

This removes the need for a lot of boilerplate code in the soc code to
hook up device_operations to devices.

Change-Id: I2afc1855407910f1faa9bdd4e9416dd46474658e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This commit is contained in:
Arthur Heymans 2022-09-20 14:03:28 +02:00 committed by Felix Held
parent bd15ece78a
commit 7f3807728b
9 changed files with 61 additions and 234 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
src/soc/amd/cezanne/chip.c
View File

@ -12,14 +12,7 @@
#include <types.h> #include <types.h>
#include "chip.h" #include "chip.h"
/* Supplied by i2c.c */ struct device_operations cezanne_cpu_bus_ops = {
extern struct device_operations soc_amd_i2c_mmio_ops;
/* Supplied by uart.c */
extern struct device_operations cezanne_uart_mmio_ops;
/* Supplied by emmc.c */
extern struct device_operations cezanne_emmc_mmio_ops;
struct device_operations cpu_bus_ops = {
.read_resources = noop_read_resources, .read_resources = noop_read_resources,
.set_resources = noop_set_resources, .set_resources = noop_set_resources,
.init = mp_cpu_bus_init, .init = mp_cpu_bus_init,
@ -39,50 +32,13 @@ static const char *soc_acpi_name(const struct device *dev)
return NULL; return NULL;
}; };
static struct device_operations pci_domain_ops = { struct device_operations cezanne_pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,
.scan_bus = pci_domain_scan_bus, .scan_bus = pci_domain_scan_bus,
.acpi_name = soc_acpi_name, .acpi_name = soc_acpi_name,
}; };
static void set_mmio_dev_ops(struct device *dev)
{
switch (dev->path.mmio.addr) {
case APU_I2C0_BASE:
case APU_I2C1_BASE:
case APU_I2C2_BASE:
case APU_I2C3_BASE:
dev->ops = &soc_amd_i2c_mmio_ops;
break;
case APU_UART0_BASE:
case APU_UART1_BASE:
dev->ops = &cezanne_uart_mmio_ops;
break;
case APU_EMMC_BASE:
dev->ops = &cezanne_emmc_mmio_ops;
break;
}
}
static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
switch (dev->path.type) {
case DEVICE_PATH_DOMAIN:
dev->ops = &pci_domain_ops;
break;
case DEVICE_PATH_CPU_CLUSTER:
dev->ops = &cpu_bus_ops;
break;
case DEVICE_PATH_MMIO:
set_mmio_dev_ops(dev);
break;
default:
break;
}
}
static void soc_init(void *chip_info) static void soc_init(void *chip_info)
{ {
default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
@ -101,7 +57,6 @@ static void soc_final(void *chip_info)
struct chip_operations soc_amd_cezanne_ops = { struct chip_operations soc_amd_cezanne_ops = {
CHIP_NAME("AMD Cezanne SoC") CHIP_NAME("AMD Cezanne SoC")
.enable_dev = enable_dev,
.init = soc_init, .init = soc_init,
.final = soc_final .final = soc_final
}; };

16
src/soc/amd/cezanne/chipset.cb
View File

@ -1,7 +1,9 @@
chip soc/amd/cezanne chip soc/amd/cezanne
device cpu_cluster 0 on device cpu_cluster 0 on
ops cezanne_cpu_bus_ops
end end
device domain 0 on device domain 0 on
ops cezanne_pci_domain_ops
device pci 00.0 alias gnb on end device pci 00.0 alias gnb on end
device pci 00.2 alias iommu off end device pci 00.2 alias iommu off end
@ -102,11 +104,11 @@ chip soc/amd/cezanne
device pci 18.7 alias data_fabric_7 on end device pci 18.7 alias data_fabric_7 on end
end end
device mmio 0xfedc2000 alias i2c_0 off end device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc3000 alias i2c_1 off end device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc4000 alias i2c_2 off end device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc5000 alias i2c_3 off end device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc9000 alias uart_0 off end device mmio 0xfedc9000 alias uart_0 off ops cezanne_uart_mmio_ops end
device mmio 0xfedca000 alias uart_1 off end device mmio 0xfedca000 alias uart_1 off ops cezanne_uart_mmio_ops end
device mmio 0xfedd5000 alias emmc off end device mmio 0xfedd5000 alias emmc off ops cezanne_emmc_mmio_ops end
end end

53
src/soc/amd/mendocino/chip.c
View File

@ -14,15 +14,7 @@
#include <types.h> #include <types.h>
#include "chip.h" #include "chip.h"
/* Supplied by i2c.c */ struct device_operations mendocino_cpu_bus_ops = {
extern struct device_operations soc_amd_i2c_mmio_ops;
/* Supplied by uart.c */
extern struct device_operations mendocino_uart_mmio_ops;
/* Supplied by emmc.c */
extern struct device_operations mendocino_emmc_mmio_ops;
struct device_operations cpu_bus_ops = {
.read_resources = noop_read_resources, .read_resources = noop_read_resources,
.set_resources = noop_set_resources, .set_resources = noop_set_resources,
.init = mp_cpu_bus_init, .init = mp_cpu_bus_init,
@ -42,53 +34,13 @@ static const char *soc_acpi_name(const struct device *dev)
return NULL; return NULL;
}; };
static struct device_operations pci_domain_ops = { struct device_operations mendocino_pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,
.scan_bus = pci_domain_scan_bus, .scan_bus = pci_domain_scan_bus,
.acpi_name = soc_acpi_name, .acpi_name = soc_acpi_name,
}; };
static void set_mmio_dev_ops(struct device *dev)
{
switch (dev->path.mmio.addr) {
case APU_I2C0_BASE:
case APU_I2C1_BASE:
case APU_I2C2_BASE:
case APU_I2C3_BASE:
dev->ops = &soc_amd_i2c_mmio_ops;
break;
case APU_UART0_BASE:
case APU_UART1_BASE:
case APU_UART2_BASE:
case APU_UART3_BASE:
case APU_UART4_BASE:
dev->ops = &mendocino_uart_mmio_ops;
break;
case APU_EMMC_BASE:
dev->ops = &mendocino_emmc_mmio_ops;
break;
}
}
static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
switch (dev->path.type) {
case DEVICE_PATH_DOMAIN:
dev->ops = &pci_domain_ops;
break;
case DEVICE_PATH_CPU_CLUSTER:
dev->ops = &cpu_bus_ops;
break;
case DEVICE_PATH_MMIO:
set_mmio_dev_ops(dev);
break;
default:
break;
}
}
static void soc_init(void *chip_info) static void soc_init(void *chip_info)
{ {
default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
@ -107,7 +59,6 @@ static void soc_final(void *chip_info)
struct chip_operations soc_amd_mendocino_ops = { struct chip_operations soc_amd_mendocino_ops = {
CHIP_NAME("AMD Mendocino SoC") CHIP_NAME("AMD Mendocino SoC")
.enable_dev = enable_dev,
.init = soc_init, .init = soc_init,
.final = soc_final .final = soc_final
}; };

22
src/soc/amd/mendocino/chipset_mendocino.cb
View File

@ -1,7 +1,9 @@
chip soc/amd/mendocino chip soc/amd/mendocino
device cpu_cluster 0 on device cpu_cluster 0 on
ops mendocino_cpu_bus_ops
end end
device domain 0 on device domain 0 on
ops mendocino_pci_domain_ops
device pci 00.0 alias gnb on end device pci 00.0 alias gnb on end
device pci 00.2 alias iommu off end device pci 00.2 alias iommu off end
@ -80,14 +82,14 @@ chip soc/amd/mendocino
device pci 18.7 alias data_fabric_7 on end device pci 18.7 alias data_fabric_7 on end
end end
device mmio 0xfedc2000 alias i2c_0 off end device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc3000 alias i2c_1 off end device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc4000 alias i2c_2 off end device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc5000 alias i2c_3 off end device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc9000 alias uart_0 off end device mmio 0xfedc9000 alias uart_0 off ops mendocino_uart_mmio_ops end
device mmio 0xfedca000 alias uart_1 off end device mmio 0xfedca000 alias uart_1 off ops mendocino_uart_mmio_ops end
device mmio 0xfedce000 alias uart_2 off end device mmio 0xfedce000 alias uart_2 off ops mendocino_uart_mmio_ops end
device mmio 0xfedcf000 alias uart_3 off end device mmio 0xfedcf000 alias uart_3 off ops mendocino_uart_mmio_ops end
device mmio 0xfedd1000 alias uart_4 off end device mmio 0xfedd1000 alias uart_4 off ops mendocino_uart_mmio_ops end
device mmio 0xfedd5000 alias emmc off end device mmio 0xfedd5000 alias emmc off ops mendocino_emmc_mmio_ops end
end end

22
src/soc/amd/mendocino/chipset_rembrandt.cb
View File

@ -1,7 +1,9 @@
chip soc/amd/mendocino chip soc/amd/mendocino
device cpu_cluster 0 on device cpu_cluster 0 on
ops mendocino_cpu_bus_ops
end end
device domain 0 on device domain 0 on
ops mendocino_pci_domain_ops
device pci 00.0 alias gnb on end device pci 00.0 alias gnb on end
device pci 00.2 alias iommu off end device pci 00.2 alias iommu off end
@ -80,14 +82,14 @@ chip soc/amd/mendocino
device pci 18.7 alias data_fabric_7 on end device pci 18.7 alias data_fabric_7 on end
end end
device mmio 0xfedc2000 alias i2c_0 off end device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc3000 alias i2c_1 off end device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc4000 alias i2c_2 off end device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc5000 alias i2c_3 off end device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc9000 alias uart_0 off end device mmio 0xfedc9000 alias uart_0 off ops mendocino_uart_mmio_ops end
device mmio 0xfedca000 alias uart_1 off end device mmio 0xfedca000 alias uart_1 off ops mendocino_uart_mmio_ops end
device mmio 0xfedce000 alias uart_2 off end device mmio 0xfedce000 alias uart_2 off ops mendocino_uart_mmio_ops end
device mmio 0xfedcf000 alias uart_3 off end device mmio 0xfedcf000 alias uart_3 off ops mendocino_uart_mmio_ops end
device mmio 0xfedd1000 alias uart_4 off end device mmio 0xfedd1000 alias uart_4 off ops mendocino_uart_mmio_ops end
device mmio 0xfedd5000 alias emmc off end device mmio 0xfedd5000 alias emmc off ops mendocino_emmc_mmio_ops end
end end

52
src/soc/amd/morgana/chip.c
View File

@ -14,14 +14,7 @@
#include <types.h> #include <types.h>
#include "chip.h" #include "chip.h"
/* Supplied by i2c.c */ struct device_operations morgana_cpu_bus_ops = {
extern struct device_operations soc_amd_i2c_mmio_ops;
/* Supplied by uart.c */
extern struct device_operations morgana_uart_mmio_ops;
/* Supplied by emmc.c */
extern struct device_operations morgana_emmc_mmio_ops;
struct device_operations cpu_bus_ops = {
.read_resources = noop_read_resources, .read_resources = noop_read_resources,
.set_resources = noop_set_resources, .set_resources = noop_set_resources,
.init = mp_cpu_bus_init, .init = mp_cpu_bus_init,
@ -41,53 +34,13 @@ static const char *soc_acpi_name(const struct device *dev)
return NULL; return NULL;
}; };
static struct device_operations pci_domain_ops = { struct device_operations morgana_pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,
.scan_bus = pci_domain_scan_bus, .scan_bus = pci_domain_scan_bus,
.acpi_name = soc_acpi_name, .acpi_name = soc_acpi_name,
}; };
static void set_mmio_dev_ops(struct device *dev)
{
switch (dev->path.mmio.addr) {
case APU_I2C0_BASE:
case APU_I2C1_BASE:
case APU_I2C2_BASE:
case APU_I2C3_BASE:
dev->ops = &soc_amd_i2c_mmio_ops;
break;
case APU_UART0_BASE:
case APU_UART1_BASE:
case APU_UART2_BASE:
case APU_UART3_BASE:
case APU_UART4_BASE:
dev->ops = &morgana_uart_mmio_ops;
break;
case APU_EMMC_BASE:
dev->ops = &morgana_emmc_mmio_ops;
break;
}
}
static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
switch (dev->path.type) {
case DEVICE_PATH_DOMAIN:
dev->ops = &pci_domain_ops;
break;
case DEVICE_PATH_CPU_CLUSTER:
dev->ops = &cpu_bus_ops;
break;
case DEVICE_PATH_MMIO:
set_mmio_dev_ops(dev);
break;
default:
break;
}
}
static void soc_init(void *chip_info) static void soc_init(void *chip_info)
{ {
default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
@ -106,7 +59,6 @@ static void soc_final(void *chip_info)
struct chip_operations soc_amd_morgana_ops = { struct chip_operations soc_amd_morgana_ops = {
CHIP_NAME("AMD Morgana SoC") CHIP_NAME("AMD Morgana SoC")
.enable_dev = enable_dev,
.init = soc_init, .init = soc_init,
.final = soc_final .final = soc_final
}; };

22
src/soc/amd/morgana/chipset.cb
View File

@ -2,8 +2,10 @@
chip soc/amd/morgana chip soc/amd/morgana
device cpu_cluster 0 on device cpu_cluster 0 on
ops morgana_cpu_bus_ops
end end
device domain 0 on device domain 0 on
ops morgana_pci_domain_ops
device pci 00.0 alias gnb on end device pci 00.0 alias gnb on end
device pci 00.2 alias iommu off end device pci 00.2 alias iommu off end
@ -82,14 +84,14 @@ chip soc/amd/morgana
device pci 18.7 alias data_fabric_7 on end device pci 18.7 alias data_fabric_7 on end
end end
device mmio 0xfedc2000 alias i2c_0 off end device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc3000 alias i2c_1 off end device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc4000 alias i2c_2 off end device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc5000 alias i2c_3 off end device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc9000 alias uart_0 off end device mmio 0xfedc9000 alias uart_0 off ops morgana_uart_mmio_ops end
device mmio 0xfedca000 alias uart_1 off end device mmio 0xfedca000 alias uart_1 off ops morgana_uart_mmio_ops end
device mmio 0xfedce000 alias uart_2 off end device mmio 0xfedce000 alias uart_2 off ops morgana_uart_mmio_ops end
device mmio 0xfedcf000 alias uart_3 off end device mmio 0xfedcf000 alias uart_3 off ops morgana_uart_mmio_ops end
device mmio 0xfedd1000 alias uart_4 off end device mmio 0xfedd1000 alias uart_4 off ops morgana_uart_mmio_ops end
device mmio 0xfedd5000 alias emmc off end device mmio 0xfedd5000 alias emmc off ops morgana_emmc_mmio_ops end
end end

45
src/soc/amd/picasso/chip.c
View File

@ -13,12 +13,7 @@
#include "chip.h" #include "chip.h"
#include <fsp/api.h> #include <fsp/api.h>
/* Supplied by i2c.c */ struct device_operations picasso_cpu_bus_ops = {
extern struct device_operations soc_amd_i2c_mmio_ops;
/* Supplied by uart.c */
extern struct device_operations picasso_uart_mmio_ops;
struct device_operations cpu_bus_ops = {
.read_resources = noop_read_resources, .read_resources = noop_read_resources,
.set_resources = noop_set_resources, .set_resources = noop_set_resources,
.init = mp_cpu_bus_init, .init = mp_cpu_bus_init,
@ -38,48 +33,13 @@ static const char *soc_acpi_name(const struct device *dev)
return NULL; return NULL;
}; };
static struct device_operations pci_domain_ops = { struct device_operations picasso_pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,
.scan_bus = pci_domain_scan_bus, .scan_bus = pci_domain_scan_bus,
.acpi_name = soc_acpi_name, .acpi_name = soc_acpi_name,
}; };
static void set_mmio_dev_ops(struct device *dev)
{
switch (dev->path.mmio.addr) {
case APU_I2C2_BASE:
case APU_I2C3_BASE:
case APU_I2C4_BASE:
dev->ops = &soc_amd_i2c_mmio_ops;
break;
case APU_UART0_BASE:
case APU_UART1_BASE:
case APU_UART2_BASE:
case APU_UART3_BASE:
dev->ops = &picasso_uart_mmio_ops;
break;
}
}
static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
switch (dev->path.type) {
case DEVICE_PATH_DOMAIN:
dev->ops = &pci_domain_ops;
break;
case DEVICE_PATH_CPU_CLUSTER:
dev->ops = &cpu_bus_ops;
break;
case DEVICE_PATH_MMIO:
set_mmio_dev_ops(dev);
break;
default:
break;
}
}
static void soc_init(void *chip_info) static void soc_init(void *chip_info)
{ {
default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
@ -97,7 +57,6 @@ static void soc_final(void *chip_info)
struct chip_operations soc_amd_picasso_ops = { struct chip_operations soc_amd_picasso_ops = {
CHIP_NAME("AMD Picasso SOC") CHIP_NAME("AMD Picasso SOC")
.enable_dev = enable_dev,
.init = soc_init, .init = soc_init,
.final = soc_final .final = soc_final
}; };

14
src/soc/amd/picasso/chipset.cb
View File

@ -2,8 +2,10 @@
chip soc/amd/picasso chip soc/amd/picasso
device cpu_cluster 0 on device cpu_cluster 0 on
ops picasso_cpu_bus_ops
end end
device domain 0 on device domain 0 on
ops picasso_pci_domain_ops
device pci 00.0 alias gnb on end device pci 00.0 alias gnb on end
device pci 00.2 alias iommu off end device pci 00.2 alias iommu off end
device pci 01.0 on end # Dummy Host Bridge, do not disable device pci 01.0 on end # Dummy Host Bridge, do not disable
@ -43,10 +45,10 @@ chip soc/amd/picasso
device pci 18.7 alias data_fabric_7 on end device pci 18.7 alias data_fabric_7 on end
end end
device mmio 0xfedc4000 alias i2c_2 off end device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc5000 alias i2c_3 off end device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc9000 alias uart_0 off end device mmio 0xfedc9000 alias uart_0 off ops picasso_uart_mmio_ops end
device mmio 0xfedca000 alias uart_1 off end device mmio 0xfedca000 alias uart_1 off ops picasso_uart_mmio_ops end
device mmio 0xfedce000 alias uart_2 off end device mmio 0xfedce000 alias uart_2 off ops picasso_uart_mmio_ops end
device mmio 0xfedcf000 alias uart_3 off end device mmio 0xfedcf000 alias uart_3 off ops picasso_uart_mmio_ops end
end end