diff --git a/src/mainboard/google/zoombini/Kconfig b/src/mainboard/google/zoombini/Kconfig
deleted file mode 100644
index 249b028340..0000000000
--- a/src/mainboard/google/zoombini/Kconfig
+++ /dev/null
@@ -1,115 +0,0 @@
-
-config BOARD_GOOGLE_BASEBOARD_ZOOMBINI
-	def_bool n
-	select BOARD_ROMSIZE_KB_16384
-	select DRIVERS_I2C_GENERIC
-	select DRIVERS_I2C_HID
-	select DRIVERS_I2C_MAX98373
-	select DRIVERS_SPI_ACPI
-	select EC_GOOGLE_CHROMEEC
-	select EC_GOOGLE_CHROMEEC_BOARDID
-	select EC_GOOGLE_CHROMEEC_LPC
-	select HAVE_ACPI_RESUME
-	select HAVE_ACPI_TABLES
-	select MAINBOARD_HAS_CHROMEOS
-	select SOC_INTEL_CANNONLAKE
-	select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
-
-if BOARD_GOOGLE_BASEBOARD_ZOOMBINI
-
-config BASEBOARD_ZOOMBINI_LAPTOP
-	def_bool n
-	select SYSTEM_TYPE_LAPTOP
-
-config DEVICETREE
-	string
-	default "variants/meowth/devicetree.cb" if BOARD_GOOGLE_MEOWTH
-	default "variants/baseboard/devicetree.cb"
-
-config DIMM_SPD_SIZE
-	int
-	default 512
-
-config DRIVER_TPM_I2C_BUS
-	depends on ZOOMBINI_USE_I2C_TPM
-	default 0x1
-
-config DRIVER_TPM_I2C_ADDR
-	depends on ZOOMBINI_USE_I2C_TPM
-	default 0x50
-
-config DRIVER_TPM_SPI_BUS
-	depends on ZOOMBINI_USE_SPI_TPM
-	default 0x1
-
-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "MEOWTH TEST 5868" if BOARD_GOOGLE_MEOWTH
-	default "ZOOMBINI TEST 5722" if BOARD_GOOGLE_ZOOMBINI
-
-config MAINBOARD_DIR
-	string
-	default "google/zoombini"
-
-config MAINBOARD_FAMILY
-	string
-	default "Google_Meowth" if BOARD_GOOGLE_MEOWTH
-	default "Google_Zoombini" if BOARD_GOOGLE_ZOOMBINI
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Meowth" if BOARD_GOOGLE_MEOWTH
-	default "Zoombini" if BOARD_GOOGLE_ZOOMBINI
-
-config MAINBOARD_VENDOR
-	string
-	default "Google"
-
-config INCLUDE_SND_MAX98357_DA7219_NHLT
-	bool "Include blobs for audio with MAX98357_DA7219"
-	select NHLT_DMIC_4CH_16B
-	select NHLT_DMIC_2CH_16B
-	select NHLT_DA7219
-	select NHLT_MAX98357
-
-config INCLUDE_SND_MAX98373_NHLT
-	bool "Include blobs for audio with MAX98373"
-	select NHLT_DMIC_4CH_16B
-	select NHLT_DMIC_2CH_16B
-	select NHLT_MAX98373
-
-config MAX_CPUS
-	int
-	default 4
-
-config VARIANT_DIR
-	string
-	default "meowth" if BOARD_GOOGLE_MEOWTH
-	default "zoombini" if BOARD_GOOGLE_ZOOMBINI
-
-config VBOOT
-	select EC_GOOGLE_CHROMEEC_SWITCHES
-	select HAS_RECOVERY_MRC_CACHE
-	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
-	select VBOOT_LID_SWITCH if BASEBOARD_ZOOMBINI_LAPTOP
-
-# Select this option to enable use of cr50 I2C TPM on zoombini.
-config ZOOMBINI_USE_I2C_TPM
-	bool
-	default n
-	select MAINBOARD_HAS_I2C_TPM_CR50
-	select MAINBOARD_HAS_TPM2
-
-# Select this option to enable use of cr50 SPI TPM on zoombini.
-config ZOOMBINI_USE_SPI_TPM
-	bool
-	default y
-	select MAINBOARD_HAS_SPI_TPM_CR50
-	select MAINBOARD_HAS_TPM2
-
-config TPM_TIS_ACPI_INTERRUPT
-	int
-	default 76 # GPE0_DW2_12 (GPP_C12)
-
-endif # BOARD_GOOGLE_BASEBOARD_ZOOMBINI
diff --git a/src/mainboard/google/zoombini/Kconfig.name b/src/mainboard/google/zoombini/Kconfig.name
deleted file mode 100644
index 6d4adcc9fb..0000000000
--- a/src/mainboard/google/zoombini/Kconfig.name
+++ /dev/null
@@ -1,11 +0,0 @@
-comment "Zoombini"
-
-config BOARD_GOOGLE_ZOOMBINI
-	bool "->  Zoombini"
-	select BOARD_GOOGLE_BASEBOARD_ZOOMBINI
-	select BASEBOARD_ZOOMBINI_LAPTOP
-
-config BOARD_GOOGLE_MEOWTH
-	bool "->  Meowth"
-	select BOARD_GOOGLE_BASEBOARD_ZOOMBINI
-	select BASEBOARD_ZOOMBINI_LAPTOP
diff --git a/src/mainboard/google/zoombini/Makefile.inc b/src/mainboard/google/zoombini/Makefile.inc
deleted file mode 100644
index d4e9fd4b4f..0000000000
--- a/src/mainboard/google/zoombini/Makefile.inc
+++ /dev/null
@@ -1,40 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2018 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-bootblock-y += bootblock.c
-bootblock-$(CONFIG_CHROMEOS) += chromeos.c
-bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
-
-verstage-$(CONFIG_CHROMEOS) += chromeos.c
-
-romstage-$(CONFIG_CHROMEOS) += chromeos.c
-romstage-y += memory.c
-romstage-y += romstage.c
-
-ramstage-$(CONFIG_CHROMEOS) += chromeos.c
-ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
-ramstage-y += mainboard.c
-ramstage-y += ramstage.c
-
-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-
-subdirs-y += variants/baseboard
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
-
-subdirs-y += variants/$(VARIANT_DIR)
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
-subdirs-y += variants/$(VARIANT_DIR)/spd
-
-subdirs-y += spd
diff --git a/src/mainboard/google/zoombini/acpi_tables.c b/src/mainboard/google/zoombini/acpi_tables.c
deleted file mode 100644
index e69de29bb2..0000000000
diff --git a/src/mainboard/google/zoombini/board_info.txt b/src/mainboard/google/zoombini/board_info.txt
deleted file mode 100644
index 3ed5a7e65c..0000000000
--- a/src/mainboard/google/zoombini/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Vendor name: Google
-Board name: Zoombini Cannonlake Reference Board
-Category: laptop
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/google/zoombini/bootblock.c b/src/mainboard/google/zoombini/bootblock.c
deleted file mode 100644
index 5f37206728..0000000000
--- a/src/mainboard/google/zoombini/bootblock.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <baseboard/gpio.h>
-#include <baseboard/variants.h>
-#include <bootblock_common.h>
-#include <soc/gpio.h>
-
-static void early_config_gpio(void)
-{
-	const struct pad_config *early_gpio_table;
-	size_t num_gpios = 0;
-
-	early_gpio_table = variant_early_gpio_table(&num_gpios);
-	gpio_configure_pads(early_gpio_table, num_gpios);
-}
-
-void bootblock_mainboard_init(void)
-{
-	early_config_gpio();
-}
diff --git a/src/mainboard/google/zoombini/chromeos.c b/src/mainboard/google/zoombini/chromeos.c
deleted file mode 100644
index 730e2c4d95..0000000000
--- a/src/mainboard/google/zoombini/chromeos.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <baseboard/gpio.h>
-#include <boot/coreboot_tables.h>
-#include <gpio.h>
-#include <rules.h>
-#include <soc/gpio.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
-	struct lb_gpio chromeos_gpios[] = {
-		{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
-		{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
-		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
-		{-1, ACTIVE_HIGH, 0, "power"},
-		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
-		/* always report back 0 as temp workaround for b:74215817 */
-		{GPIO_EC_IN_RW, ACTIVE_HIGH, 0, "EC in RW"},
-	};
-	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-}
-
-int get_write_protect_state(void)
-{
-	/* Read PCH_WP GPIO. */
-	return gpio_get(GPIO_PCH_WP);
-}
-
-static const struct cros_gpio cros_gpios[] = {
-	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
-	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
-};
-
-void mainboard_chromeos_acpi_generate(void)
-{
-	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
-}
diff --git a/src/mainboard/google/zoombini/chromeos.fmd b/src/mainboard/google/zoombini/chromeos.fmd
deleted file mode 100644
index 7123a5f9ad..0000000000
--- a/src/mainboard/google/zoombini/chromeos.fmd
+++ /dev/null
@@ -1,44 +0,0 @@
-FLASH@0xff000000 0x1000000 {
-	SI_ALL@0x0 0x300000 {
-		SI_DESC@0x0 0x1000
-		SI_ME@0x1000 0x2ff000
-	}
-	SI_BIOS@0x300000 0xd00000 {
-		RW_SECTION_A@0x0 0x368000 {
-			VBLOCK_A@0x0 0x10000
-			FW_MAIN_A(CBFS)@0x10000 0x357fc0
-			RW_FWID_A@0x367fc0 0x40
-		}
-		RW_SECTION_B@0x368000 0x368000 {
-			VBLOCK_B@0x0 0x10000
-			FW_MAIN_B(CBFS)@0x10000 0x357fc0
-			RW_FWID_B@0x367fc0 0x40
-		}
-		RW_MISC@0x6d0000 0x30000 {
-			UNIFIED_MRC_CACHE@0x0 0x20000 {
-				RECOVERY_MRC_CACHE@0x0 0x10000
-				RW_MRC_CACHE@0x10000 0x10000
-			}
-			RW_ELOG@0x20000 0x4000
-			RW_SHARED@0x24000 0x4000 {
-				SHARED_DATA@0x0 0x2000
-				VBLOCK_DEV@0x2000 0x2000
-			}
-			RW_VPD@0x28000 0x2000
-			RW_NVRAM@0x2a000 0x6000
-		}
-		SMMSTORE@0x700000 0x40000
-		RW_LEGACY(CBFS)@0x740000 0x1c0000
-		WP_RO@0x900000 0x400000 {
-			RO_VPD@0x0 0x4000
-			RO_UNUSED@0x4000 0xc000
-			RO_SECTION@0x10000 0x3f0000 {
-				FMAP@0x0 0x800
-				RO_FRID@0x800 0x40
-				RO_FRID_PAD@0x840 0x7c0
-				GBB@0x1000 0xef000
-				COREBOOT(CBFS)@0xf0000 0x300000
-			}
-		}
-	}
-}
diff --git a/src/mainboard/google/zoombini/dsdt.asl b/src/mainboard/google/zoombini/dsdt.asl
deleted file mode 100644
index e9988f097e..0000000000
--- a/src/mainboard/google/zoombini/dsdt.asl
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright 2017 Google Inc.
- * Copyright (C) 2017 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "variant/ec.h"
-#include "variant/gpio.h"
-
-#include <arch/acpi.h>
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	0x02,		// DSDT revision: ACPI v2.0 and up
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x20110725	// OEM revision
-)
-{
-	// Some generic macros
-	#include <soc/intel/cannonlake/acpi/platform.asl>
-
-	// global NVS and variables
-	#include <soc/intel/cannonlake/acpi/globalnvs.asl>
-
-	// CPU
-	#include <cpu/intel/common/acpi/cpu.asl>
-
-	Scope (\_SB) {
-		Device (PCI0)
-		{
-			#include <soc/intel/cannonlake/acpi/northbridge.asl>
-			#include <soc/intel/cannonlake/acpi/southbridge.asl>
-		}
-	}
-
-	#if IS_ENABLED(CONFIG_CHROMEOS)
-	// Chrome OS specific
-	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
-	#endif
-
-	// Chipset specific sleep states
-	#include <soc/intel/cannonlake/acpi/sleepstates.asl>
-
-	/* Chrome OS Embedded Controller */
-	Scope (\_SB.PCI0.LPCB)
-	{
-		/* ACPI code for EC SuperIO functions */
-		#include <ec/google/chromeec/acpi/superio.asl>
-		/* ACPI code for EC functions */
-		#include <ec/google/chromeec/acpi/ec.asl>
-	}
-}
diff --git a/src/mainboard/google/zoombini/ec.c b/src/mainboard/google/zoombini/ec.c
deleted file mode 100644
index d756444e15..0000000000
--- a/src/mainboard/google/zoombini/ec.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <ec/google/chromeec/ec.h>
-#include <variant/ec.h>
-
-void mainboard_ec_init(void)
-{
-	const struct google_chromeec_event_info info = {
-		.log_events = MAINBOARD_EC_LOG_EVENTS,
-		.sci_events = MAINBOARD_EC_SCI_EVENTS,
-		.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
-		.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
-	};
-
-	google_chromeec_events_init(&info, acpi_is_wakeup_s3());
-}
diff --git a/src/mainboard/google/zoombini/mainboard.c b/src/mainboard/google/zoombini/mainboard.c
deleted file mode 100644
index 96e1ac0190..0000000000
--- a/src/mainboard/google/zoombini/mainboard.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <ec/ec.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <nhlt.h>
-#include <arch/acpi.h>
-#include <baseboard/variants.h>
-
-static void mainboard_init(struct device *dev)
-{
-	mainboard_ec_init();
-}
-
-static unsigned long mainboard_write_acpi_tables(struct device *device,
-	unsigned long current, acpi_rsdp_t *rsdp)
-{
-	uintptr_t start_addr;
-	uintptr_t end_addr;
-	struct nhlt *nhlt;
-
-	start_addr = current;
-
-	nhlt = nhlt_init();
-
-	if (nhlt == NULL)
-		return start_addr;
-
-	variant_nhlt_init(nhlt);
-
-	end_addr = nhlt_soc_serialize(nhlt, start_addr);
-
-	if (end_addr != start_addr)
-		acpi_add_table(rsdp, (void *)start_addr);
-
-	return end_addr;
-}
-
-static void mainboard_enable(struct device *dev)
-{
-	dev->ops->init = mainboard_init;
-	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
-	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/google/zoombini/memory.c b/src/mainboard/google/zoombini/memory.c
deleted file mode 100644
index 60829b10a5..0000000000
--- a/src/mainboard/google/zoombini/memory.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <baseboard/variants.h>
-#include <baseboard/gpio.h>
-#include <gpio.h>
-#include <soc/cnl_memcfg_init.h>
-
-static const struct cnl_mb_cfg baseboard_lpddr4_cfg = {
-	.dq_map[DDR_CH0] = {
-		/*
-		 * CLK0 goes to package 0 - Bytes[3:0],
-		 * CLK1 goes to package 1 - Bytes[7:4]
-		 */
-		{ 0x0F, 0xF0 },
-
-		/*
-		 * Cmd CAA goes to Bytes[3:0],
-		 * Cmd CAB goes to Bytes[7:4]
-		 */
-		{ 0x0F, 0xF0 },
-
-		/* CTL (CS) goes to all bytes */
-		{ 0xFF, 0x00 },
-	},
-
-	.dq_map[DDR_CH1] = {
-		/*
-		 * CLK0 goes to package 0 - Bytes[3:0],
-		 * CLK1 goes to package 1 - Bytes[7:4]
-		 */
-		{ 0x0F, 0xF0 },
-
-		/*
-		 * Cmd CAA goes to Bytes[3:0],
-		 * Cmd CAB goes to Bytes[7:4]
-		 */
-		{ 0x0F, 0xF0 },
-
-		/* CTL (CS) goes to all bytes */
-		{ 0xFF, 0x00 },
-	},
-
-	/*
-	 * The dqs_map arrays map the lpddr4 pins to the SoC pins
-	 * for both channels.
-	 *
-	 * the index = pin number on lpddr4 part
-	 * the value = pin number on SoC
-	 */
-	.dqs_map[DDR_CH0] = { 3, 1, 2, 0, 7, 5, 6, 4 },
-	.dqs_map[DDR_CH1] = { 3, 2, 0, 1, 7, 5, 6, 4 },
-
-	/* Baseboard uses three 100 Ohm rcomp resistors */
-	.rcomp_resistor = { 100, 100, 100 },
-
-	/*
-	 * Baseboard Rcomp target values.
-	 * Rcomp targets for baseboard should be
-	 * { 80, 40, 40, 40, 30 }, but we need to
-	 * nil out rcomp targets for now to avoid bug b:70896346
-	 */
-	.rcomp_targets = { 0, 0, 0, 0, 0 },
-
-	/* Baseboard is a non-interleaved design */
-	.dq_pins_interleaved = 0,
-
-	/* Disable Early Command Training */
-	.ect = 0,
-};
-
-const struct cnl_mb_cfg *__weak variant_lpddr4_config(void)
-{
-	return &baseboard_lpddr4_cfg;
-}
-
-size_t __weak variant_memory_sku(void)
-{
-	const gpio_t pads[] = {
-		[3] = GPIO_MEM_CONFIG_3, [2] = GPIO_MEM_CONFIG_2,
-		[1] = GPIO_MEM_CONFIG_1, [0] = GPIO_MEM_CONFIG_0,
-	};
-
-	return gpio_base2_value(pads, ARRAY_SIZE(pads));
-}
diff --git a/src/mainboard/google/zoombini/ramstage.c b/src/mainboard/google/zoombini/ramstage.c
deleted file mode 100644
index 7c73357430..0000000000
--- a/src/mainboard/google/zoombini/ramstage.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <baseboard/variants.h>
-#include <soc/ramstage.h>
-#include <variant/gpio.h>
-
-void mainboard_silicon_init_params(FSP_S_CONFIG *params)
-{
-	size_t num;
-	const struct pad_config *gpio_table;
-
-	gpio_table = variant_gpio_table(&num);
-	gpio_configure_pads(gpio_table, num);
-}
diff --git a/src/mainboard/google/zoombini/romstage.c b/src/mainboard/google/zoombini/romstage.c
deleted file mode 100644
index 4bd0ede14f..0000000000
--- a/src/mainboard/google/zoombini/romstage.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <baseboard/variants.h>
-#include <soc/cnl_memcfg_init.h>
-#include <soc/romstage.h>
-
-void mainboard_memory_init_params(FSPM_UPD *memupd)
-{
-	const struct spd_info spd = {
-		.spd_by_index = true,
-		.spd_spec.spd_index = variant_memory_sku(),
-	};
-
-	cannonlake_memcfg_init(&memupd->FspmConfig,
-				variant_lpddr4_config(), &spd);
-}
diff --git a/src/mainboard/google/zoombini/smihandler.c b/src/mainboard/google/zoombini/smihandler.c
deleted file mode 100644
index c9d08a56ad..0000000000
--- a/src/mainboard/google/zoombini/smihandler.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <cpu/x86/smm.h>
-#include <ec/google/chromeec/smm.h>
-#include <gpio.h>
-#include <soc/gpio.h>
-#include <soc/smm.h>
-#include <variant/ec.h>
-
-void mainboard_smi_espi_handler(void)
-{
-	chromeec_smi_process_events();
-}
-
-void mainboard_smi_sleep(u8 slp_typ)
-{
-	chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
-			MAINBOARD_EC_S5_WAKE_EVENTS);
-}
-
-int mainboard_smi_apmc(u8 apmc)
-{
-	chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
-			MAINBOARD_EC_SMI_EVENTS);
-	return 0;
-}
diff --git a/src/mainboard/google/zoombini/spd/Hynix_H9HCNNN8KUMLHR_1GB.spd.hex b/src/mainboard/google/zoombini/spd/Hynix_H9HCNNN8KUMLHR_1GB.spd.hex
deleted file mode 100644
index b5da9f33bb..0000000000
--- a/src/mainboard/google/zoombini/spd/Hynix_H9HCNNN8KUMLHR_1GB.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 11 10 0E 15 19 05 08 00 40 00 00 02 22 00 00
-00 00 05 FF 92 55 00 00 8C 00 90 A8 90 A0 05 D0
-02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 9E 00 A7 ED 8A
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zoombini/spd/Hynix_H9HCNNNCPUMLHR_4GB.spd.hex b/src/mainboard/google/zoombini/spd/Hynix_H9HCNNNCPUMLHR_4GB.spd.hex
deleted file mode 100644
index 1a6d90bc5d..0000000000
--- a/src/mainboard/google/zoombini/spd/Hynix_H9HCNNNCPUMLHR_4GB.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 11 10 0E 16 21 95 08 00 40 00 00 0A 22 00 00
-48 00 05 FF 92 55 00 00 A0 41 90 A8 90 A0 05 D0
-02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 7A 05
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zoombini/spd/Makefile.inc b/src/mainboard/google/zoombini/spd/Makefile.inc
deleted file mode 100644
index 0aec18d0b5..0000000000
--- a/src/mainboard/google/zoombini/spd/Makefile.inc
+++ /dev/null
@@ -1,34 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2018 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-SPD_BIN = $(obj)/spd.bin
-
-ifeq ($(SPD_SOURCES),)
-	SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this)
-else
-	SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-endif
-
-# Include spd ROM data
-$(SPD_BIN): $(SPD_DEPS)
-	for f in $+; \
-	  do for c in $$(cat $$f | grep -v ^#); \
-	    do printf $$(printf '\%o' 0x$$c); \
-	  done; \
-	done > $@
-
-cbfs-files-y += spd.bin
-spd.bin-file := $(SPD_BIN)
-spd.bin-type := spd
diff --git a/src/mainboard/google/zoombini/spd/Micron_MT53B1024M32D4_4GB.spd.hex b/src/mainboard/google/zoombini/spd/Micron_MT53B1024M32D4_4GB.spd.hex
deleted file mode 100644
index 1e28d92369..0000000000
--- a/src/mainboard/google/zoombini/spd/Micron_MT53B1024M32D4_4GB.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 11 10 OE 15 21 B5 08 00 40 00 00 0A 63 00 00
-51 00 05 FF D2 5D 01 00 A0 41 90 A8 90 A0 05 D0
-02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 7A 05
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zoombini/spd/Micron_MT53B512M32D2_2GB.spd.hex b/src/mainboard/google/zoombini/spd/Micron_MT53B512M32D2_2GB.spd.hex
deleted file mode 100644
index 87d04200fa..0000000000
--- a/src/mainboard/google/zoombini/spd/Micron_MT53B512M32D2_2GB.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 11 10 OE 15 19 95 08 00 40 00 00 0A 63 00 00
-09 00 04 00 D2 5D 05 00 89 41 90 A8 90 A0 05 D0
-02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 FB 00 23 17 9B
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zoombini/spd/Samsung_K4F6E3S4HM_2GB.spd.hex b/src/mainboard/google/zoombini/spd/Samsung_K4F6E3S4HM_2GB.spd.hex
deleted file mode 100644
index f4c330a898..0000000000
--- a/src/mainboard/google/zoombini/spd/Samsung_K4F6E3S4HM_2GB.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 10 0E 15 19 95 08 00 40 00 00 02 22 00 00
-48 00 05 FF 92 55 00 00 8C 00 90 A8 90 A0 05 D0
-02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zoombini/spd/Samsung_K4F8E304HB_1GB.spd.hex b/src/mainboard/google/zoombini/spd/Samsung_K4F8E304HB_1GB.spd.hex
deleted file mode 100644
index bf5e261dbe..0000000000
--- a/src/mainboard/google/zoombini/spd/Samsung_K4F8E304HB_1GB.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 10 0E 15 19 04 08 00 00 00 00 02 22 00 00
-48 00 05 0f 92 54 01 00 8A 00 90 A8 90 A0 05 D0
-02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 92 00 A7 E3 B5
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 4B 34 46 38 45 33 30
-34 48 42 2D 4D 47 43 6A 00 00 00 00 00 00 80 CE
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zoombini/variants/baseboard/Makefile.inc b/src/mainboard/google/zoombini/variants/baseboard/Makefile.inc
deleted file mode 100644
index d81101ab64..0000000000
--- a/src/mainboard/google/zoombini/variants/baseboard/Makefile.inc
+++ /dev/null
@@ -1,19 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2017 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-bootblock-y += gpio.c
-
-ramstage-y += gpio.c
-ramstage-y += nhlt.c
diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
deleted file mode 100644
index 36c6595feb..0000000000
--- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
+++ /dev/null
@@ -1,129 +0,0 @@
-chip soc/intel/cannonlake
-
-	# GPE configuration
-	# Note that GPE events called out in ASL code rely on this
-	# route. i.e. If this route changes then the affected GPE
-	# offset bits also need to be changed.
-	register "gpe0_dw0" = "PMC_GPP_A"
-	register "gpe0_dw1" = "PMC_GPP_B"
-	register "gpe0_dw2" = "PMC_GPP_C"
-
-	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
-	register "gen1_dec" = "0x00fc0801"
-	register "gen2_dec" = "0x000c0201"
-	# EC memory map range is 0x900-0x9ff
-	register "gen3_dec" = "0x00fc0901"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-
-	# FSP configuration
-	register "SaGv" = "3"
-	register "ScsEmmcHs400Enabled" = "1"
-
-	# Intel Common SoC Config
-	#+-------------------+---------------------------+
-	#| Field             |  Value                    |
-	#+-------------------+---------------------------+
-	#| GSPI0             | cr50 TPM. Early init is   |
-	#|                   | required to set up a BAR  |
-	#|                   | for TPM communication     |
-	#|                   | before memory is up       |
-	#+-------------------+---------------------------+
-	register "common_soc_config" = "{
-		.gspi[0] = {
-			.speed_mhz = 1,
-			.early_init = 1,
-		},
-	}"
-
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
-	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"
-	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"
-	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-	register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-	register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-	register "usb2_ports[6]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-	register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-	register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-	register "usb2_ports[9]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
-
-	# Enable Root port 8 (PCIe port 9) for NVMe
-	register "PcieRpEnable[8]" = "1"
-	register "PcieClkSrcUsage[3]" = "8"
-	register "PcieClkSrcClkReq[3]" = "3"
-
-	device domain 0 on
-		device pci 00.0 on  end # Host Bridge
-		device pci 02.0 on  end # Integrated Graphics Device
-		device pci 04.0 on  end # SA Thermal device
-		device pci 12.0 on  end # Thermal Subsystem
-		device pci 12.5 off end # UFS SCS
-		device pci 12.6 off end # GSPI #2
-		device pci 14.0 on  end # USB xHCI
-		device pci 14.1 off end # USB xDCI (OTG)
-		chip drivers/intel/wifi
-			register "wake" = "PME_B0_EN_BIT"
-			device pci 14.3 on  end # CNVi wifi
-		end
-		device pci 14.5 on  end # SDCard
-		device pci 15.0 on  end # I2C #0
-		device pci 15.1 on  end # I2C #1
-		device pci 15.2 on  end # I2C #2
-		device pci 15.3 on  end # I2C #3
-		device pci 16.0 on  end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT Redirection
-		device pci 16.4 off end # Management Engine Interface 3
-		device pci 16.5 off end # Management Engine Interface 4
-		device pci 17.0 off end # SATA
-		device pci 19.0 on  end # I2C #4
-		device pci 19.1 on  end # I2C #5
-		device pci 19.2 off end # UART #2
-		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 off end # PCI Express Port 13
-		device pci 1d.5 off end # PCI Express Port 14
-		device pci 1d.6 off end # PCI Express Port 15
-		device pci 1d.7 off end # PCI Express Port 16
-		device pci 1e.0 on  end # UART #0
-		device pci 1e.1 off end # UART #1
-		device pci 1e.2 on
-			chip drivers/spi/acpi
-				register "hid" = "ACPI_DT_NAMESPACE_HID"
-				register "compat_string" = ""google,cr50""
-				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C12_IRQ)"
-				device spi 0 on end
-			end
-		end # GSPI #0
-		device pci 1e.3 on  end # GSPI #1
-		device pci 1f.0 on
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end # LPC Interface
-		device pci 1f.1 on  end # P2SB
-		device pci 1f.2 on  end # Power Management Controller
-		device pci 1f.3 on  end # Intel HDA
-		device pci 1f.4 on  end # SMBus
-		device pci 1f.5 on  end # PCH SPI
-		device pci 1f.6 off end # GbE
-	end
-end
diff --git a/src/mainboard/google/zoombini/variants/baseboard/gpio.c b/src/mainboard/google/zoombini/variants/baseboard/gpio.c
deleted file mode 100644
index 54474053ad..0000000000
--- a/src/mainboard/google/zoombini/variants/baseboard/gpio.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
- * GNU General Public License for more details.
- */
-
-#include <baseboard/gpio.h>
-#include <baseboard/variants.h>
-
-/* Pad configuration in ramstage */
-static const struct pad_config gpio_table[] = {
-/* RCIN# */		PAD_CFG_GPI(GPP_A0, NONE, DEEP), /* PCH_CSI_GPIO1 */
-/* ESPI_IO0 */
-/* ESPI_IO1 */
-/* ESPI_IO2 */
-/* ESPI_IO3 */
-/* ESPI_CS# */
-/* SERIRQ */		PAD_CFG_GPI(GPP_A6, NONE, DEEP), /* PCH_CSI_GPIO2 */
-/* PIRQA# */		PAD_NC(GPP_A7, NONE), /* PCH_CSI_GPIO1 */
-/* CLKRUN# */		PAD_CFG_GPI(GPP_A8, NONE, DEEP), /* EC_IN_RW_OD */
-/* ESPI_CLK */
-/* CLKOUT_LPC1 */	PAD_CFG_GPO(GPP_A10, 0, DEEP), /* PEN_RESET_ODL */
-/* PME# */		PAD_NC(GPP_A11, NONE),
-/* BM_BUSY# */		PAD_CFG_GPI(GPP_A12, UP_20K, DEEP), /* FPMCU_INT */
-/* SUSWARN# */
-/* ESPI_RESET# */
-/* SUSACK# */
-/* SD_1P8_SEL */	PAD_NC(GPP_A16, NONE),
-/* SD_PWR_EN# */
-/* ISH_GP0 */		PAD_CFG_GPO(GPP_A18, 0, DEEP),
-					/* GNSS_DISABLE_1V8_ODL */
-/* ISH_GP1 */		PAD_CFG_GPO(GPP_A19, 0, DEEP),
-					/* WWAN_RADIO_DISABLE_1V8_ODL */
-/* ISH_GP2 */		PAD_CFG_GPI(GPP_A20, NONE, DEEP), /* GP_INT_ODL */
-/* ISH_GP3 */		PAD_CFG_GPI(GPP_A21, NONE, DEEP), /* FPMCU_PCH_BOOT0 */
-/* ISH_GP4 */		PAD_CFG_GPI(GPP_A22, UP_20K, DEEP), /* FPMCU_INT */
-/* ISH_GP5 */		PAD_CFG_GPO(GPP_A23, 0, DEEP), /* FPMCU_RST_ODL */
-/* CORE_VID0 */		PAD_NC(GPP_B0, NONE),
-/* CORE_VID1 */		PAD_NC(GPP_B1, NONE),
-/* VRALERT# */		PAD_NC(GPP_B2, NONE),
-/* CPU_GP2 */		PAD_NC(GPP_B3, NONE),
-/* CPU_GP3 */		PAD_NC(GPP_B4, NONE),
-/* SRCCLKREQ0# */	PAD_NC(GPP_B5, NONE),
-/* SRCCLKREQ1# */
-/* SRCCLKREQ2# */
-/* SRCCLKREQ3# */
-/* SRCCLKREQ4# */	PAD_NC(GPP_B9, NONE),
-/* SRCCLKREQ5# */	PAD_NC(GPP_B10, NONE),
-/* EXT_PWR_GATE# */
-/* SLP_S0# */
-/* PLTRST# */
-/* SPKR */		PAD_NC(GPP_B14, DN_20K), /* GPP_B14_STRAP */
-#if IS_ENABLED(CONFIG_ZOOMBINI_USE_SPI_TPM)
-/* GSPI0_CS# */		/* H1_SLAVE_SPI_CS_L */
-/* GSPI0_CLK */		/* H1_SLAVE_SPI_CLK_R */
-/* GSPI0_MISO */	/* H1_SLAVE_SPI_MISO_R */
-/* GSPI0_MOSI */	/* H1_SLAVE_SPI_MOSI_R */
-#else
-/* GSPI0_CS# */		PAD_NC(GPP_B15, NONE),
-/* GSPI0_CLK */		PAD_NC(GPP_B16, NONE),
-/* GSPI0_MISO */	PAD_NC(GPP_B17, NONE),
-/* GSPI0_MOSI */	PAD_NC(GPP_B18, NONE),
-#endif
-/* GSPI1_CS# */
-/* GSPI1_CLK */
-/* GSPI1_MISO */
-/* GSPI1_MOSI */
-/* SML1ALERT# */	PAD_NC(GPP_B23, DN_20K), /* GPP_B23_STRAP */
-/* SMBCLK */		PAD_CFG_GPO(GPP_C0, 0, DEEP), /* SOC_EDP_CABC_EN */
-/* SMBDATA */		PAD_CFG_GPI(GPP_C1, NONE, DEEP),
-					/* PCIE_8_WLAN_WAKE_ODL */
-/* SMBALERT# */		PAD_NC(GPP_C2, DN_20K), /* GPP_C2_STRAP - 20K_PD */
-/* SML0CLK */		PAD_CFG_GPO(GPP_C3, 0, DEEP),
-					/* EN_PP3300_TRACKPAD */
-/* SML0DATA */		PAD_NC(GPP_C4, NONE),
-/* SML0ALERT# */	PAD_NC(GPP_C5, DN_20K), /* GPP_C5_STRAP - 20K_PD */
-/* SM1CLK */		PAD_CFG_GPI(GPP_C6, NONE, DEEP), /* PEN_PDCT_ODL */
-/* SM1DATA */		PAD_CFG_GPI(GPP_C7, NONE, DEEP), /* PEN_INT_ODL */
-/* UART0_RXD */
-/* UART0_TXD */
-/* UART0_RTS# */	PAD_NC(GPP_C10, NONE),
-/* UART0_CTS# */	PAD_NC(GPP_C11, NONE),
-/* UART1_RXD */         PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_SINGLE,
-					 INVERT), /* H1_PCH_INT_ODL */
-/* UART1_TXD */		PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* TRACKPAD_INT_ODL */
-/* UART1_RTS# */	PAD_CFG_GPI(GPP_C14, NONE, DEEP),
-					/* TOUCHSCREEN_INT_ODL */
-/* UART1_CTS# */	PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* TRACKPAD_INT_ODL */
-/* I2C0_SDA */
-/* I2C0_SCL */
-/* I2C1_SDA */
-/* I2C1_SCL */
-/* UART2_RXD */		PAD_NC(GPP_C20, NONE),
-/* UART2_TXD */		PAD_NC(GPP_C21, NONE),
-/* UART2_RTS# */	PAD_NC(GPP_C22, NONE),
-/* UART2_CTS# */	PAD_NC(GPP_C23, NONE),
-/* SPI1_CS# */		PAD_CFG_GPI(GPP_D0, NONE, DEEP), /* PCH_MEM_STRAP3 */
-/* SPI1_CLK */		PAD_NC(GPP_D1, NONE),
-/* SPI1_MISO */		PAD_NC(GPP_D2, NONE),
-/* SPI1_MOSI */		PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* PCH_MEM_STRAP0 */
-/* FASHTRIG */
-/* ISH_I2C0_SDA */	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
-					/* EC_I2C_SENSOR_SDA */
-/* ISH_I2C0_SCL */	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
-					/* EC_I2C_SENSOR_SCL */
-/* ISH_I2C1_SDA */	PAD_CFG_GPI(GPP_D7, NONE, DEEP), /* WWAN_SAR_INT_ODL */
-/* ISH_I2C1_SCL */	PAD_NC(GPP_D8, NONE),
-/* ISH_SPI_CS# */	PAD_CFG_GPO(GPP_D9, 0, DEEP),
-					/* EN_PP3300_TOUCHSCREEN */
-/* ISH_SPI_CLK */	PAD_CFG_GPO(GPP_D10, 0, DEEP), /* EN_PP3300_WLAN */
-/* ISH_SPI_MISO */	PAD_CFG_GPO(GPP_D11, 0, DEEP), /* EN_PP3300_WWAN */
-/* ISH_SPI_MOSI */	PAD_CFG_GPI(GPP_D12, NONE, DEEP), /* GPP_D12_STRAP */
-/* ISH_UART0_RXD */	PAD_NC(GPP_D13, NONE), /* ISH_UART_RX */
-/* ISH_UART0_TXD */	PAD_NC(GPP_D14, NONE), /* ISH_UART_TX */
-/* ISH_UART0_RTS# */	PAD_CFG_GPO(GPP_D15, 0, DEEP),
-					/* TOUCHSCREEN_RST_ODL */
-/* ISH_UART0_CTS# */	PAD_CFG_GPO(GPP_D16, 0, DEEP), /* SPK_PA_EN */
-/* DMIC_CLK1 */		PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
-					/* BASE_CAM_DMIC_CLK */
-/* DMIC_DATA1 */	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
-					/* BASE_CAM_DMIC_DATA */
-/* DMIC_CLK0 */		PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
-					/* LID_CAM_DMIC_CLK */
-/* DMIC_DATA0 */	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
-					/* LID_CAM_DMIC_DATA */
-/* SPI1_IO2 */		PAD_CFG_GPI(GPP_D21, NONE, DEEP), /* PCH_MEM_STRAP1 */
-/* SPI1_IO3 */		PAD_CFG_GPI(GPP_D22, NONE, DEEP), /* PCH_MEM_STRAP2 */
-/* I2S_MCLK */
-/* SATAXPCI0 */		PAD_NC(GPP_E0, NONE), /* PCH_TP_1 */
-/* SATAXPCIE1 */	PAD_NC(GPP_E1, NONE), /* PCH_TP_2 */
-/* SATAXPCIE2 */	PAD_NC(GPP_E2, NONE), /* PCH_TP_3 */
-/* CPU_GP0 */		PAD_NC(GPP_E3, NONE),
-/* SATA_DEVSLP0 */	PAD_CFG_GPI(GPP_E4, NONE, DEEP),
-					/* PCIE_7_WWAN_WAKE_ODL */
-/* SATA_DEVSLP1 */	PAD_NC(GPP_E5, NONE),
-/* SATA_DEVSLP2 */	PAD_NC(GPP_E6, NONE),
-/* CPU_GP1 */		PAD_NC(GPP_E7, NONE),
-/* SATALED# */		PAD_NC(GPP_E8, NONE), /* PCH_TP_4 */
-/* USB2_OCO# */
-/* USB2_OC1# */
-/* USB2_OC2# */
-/* USB2_OC3# */
-/* DDPB_HPD0 */
-/* DDPC_HPD1 */		PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* USB_C1_HPD */
-/* DDPD_HPD2 */
-/* DDPE_HPD3 */		PAD_NC(GPP_E16, NONE),
-/* EDP_HPD */
-/* DDPB_CTRLCLK */	PAD_NC(GPP_E18, NONE),
-/* DDPB_CTRLDATA */	PAD_CFG_GPI(GPP_E19, DN_20K, DEEP), /* GPP_E19_STRAP */
-/* DDPC_CTRLCLK */	PAD_NC(GPP_E20, NONE),
-/* DDPC_CTRLDATA */	PAD_CFG_GPI(GPP_E21, DN_20K, DEEP), /* GPP_E21_STRAP */
-/* DDPD_CTRLCLK */	PAD_NC(GPP_E22, NONE),
-/* DDPD_CTRLDATA */	PAD_CFG_GPI(GPP_E23, DN_20K, DEEP), /* I2S2_SCLK */
-/* I2S2_SFRM */		PAD_CFG_GPO(GPP_F1, 0, DEEP),
-					/* WWAN_RESET_1V8_ODL */
-/* I2S2_TXD */		PAD_NC(GPP_F2, NONE),
-/* I2S2_RXD */		PAD_CFG_GPO(GPP_F3, 0, DEEP), /* CNV_RF_RESET_L */
-/* I2C2_SDA */
-/* I2C2_SCL */
-/* I2C3_SDA */
-/* I2C3_SCL */
-/* I2C4_SDA */
-/* I2C4_SCL */
-/* I2C5_SDA */
-/* I2C5_SCL */
-/* EMMC_CMD */
-/* EMMC_DATA0 */
-/* EMMC_DATA1 */
-/* EMMC_DATA2 */
-/* EMMC_DATA3 */
-/* EMMC_DATA4 */
-/* EMMC_DATA5 */
-/* EMMC_DATA6 */
-/* EMMC_DATA7 */
-/* EMMC_RCLK */
-/* EMMC_CLK */
-/* RSVD */		PAD_NC(GPP_F23, NONE),
-/* SD_CMD */
-/* SD_DATA0 */
-/* SD_DATA1 */
-/* SD_DATA2 */
-/* SD_DATA3 */
-/* SD_CD# */
-/* SD_CLK */
-/* SD_WP */		PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), /* SD_CD_ODL */
-/* I2S2_SCLK */		PAD_NC(GPP_H0, NONE), /* I2S2_SCLK - TP75 */
-/* I2S2_SFRM */		PAD_NC(GPP_H1, NONE), /* I2S2_SFRM - TP74 */
-/* I2S2_TXD */
-/* I2S2_RXD */		PAD_NC(GPP_H3, NONE), /* I2S2_PCH_RX TP76 */
-/* I2C2_SDA */
-/* I2C2_SCL */
-/* I2C3_SDA */
-/* I2C3_SCL */
-/* I2C4_SDA */
-/* I2C4_SCL */
-/* I2C5_SDA */
-/* I2C5_SCL */
-/* M2_SKT2_CFG0 */	PAD_NC(GPP_H12, NONE), /* PCH_TP_5 - TP60 */
-/* M2_SKT2_CFG1 */	PAD_NC(GPP_H13, NONE), /* PCH_TP_6 - TP61 */
-/* M2_SKT2_CFG2 */	PAD_NC(GPP_H14, NONE), /* PCH_TP_7 - TP62 */
-/* M2_SKT2_CFG3 */	PAD_NC(GPP_H15, NONE), /* PCH_TP_8 - TP63 */
-/* DDPF_CTRLCLK */	PAD_NC(GPP_H16, NONE),
-/* DPPF_CTRLDATA */	PAD_NC(GPP_H17, NONE),
-/* CPU_C10_GATE# */	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
-					/* CPU_C10_GATE_PCH_L */
-/* TIMESYNC0 */		PAD_NC(GPP_H19, NONE),
-/* IMGCLKOUT1 */	PAD_NC(GPP_H20, NONE),
-/* GPP_H21 */		PAD_CFG_GPI(GPP_H21, DN_20K, DEEP), /* H21_STRAP */
-/* GPP_H22 */
-/* GPP_H23 */		PAD_NC(GPP_H23, DN_20K), /* H23_STRAP */
-
-/* BATLOW# */
-/* ACPRESENT */		PAD_NC(GPD1, NONE),
-/* LAN_WAKE# */		PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_ODL */
-/* PWRBTN# */
-/* SLP_S3# */
-/* SLP_S4# */
-/* SLP_A# */		PAD_NC(GPD6, NONE),
-/* RSVD */
-/* SUSCLK */
-/* SLP_WLAN# */		PAD_NC(GPD9, NONE),
-/* SLP_S5# */		PAD_NC(GPD10, NONE),
-/* LANPHYC */		PAD_NC(GPD11, NONE),
-};
-
-/* Early pad configuration in bootblock */
-static const struct pad_config early_gpio_table[] = {
-#if IS_ENABLED(CONFIG_ZOOMBINI_USE_SPI_TPM)
-/* GSPI0_CS# */		PAD_CFG_NF(GPP_B15, NONE, DEEP,
-				   NF1), /* PCH_SPI_H1_3V3_CS_L */
-/* GSPI0_CLK */		PAD_CFG_NF(GPP_B16, NONE, DEEP,
-				   NF1), /* PCH_SPI_H1_3V3_CLK */
-/* GSPI0_MISO */	PAD_CFG_NF(GPP_B17, NONE, DEEP,
-				   NF1), /* PCH_SPI_H1_3V3_MISO */
-/* GSPI0_MOSI */	PAD_CFG_NF(GPP_B18, NONE, DEEP,
-				   NF1), /* PCH_SPI_H1_3V3_MOSI */
-#endif
-#if IS_ENABLED(CONFIG_ZOOMBINI_USE_I2C_TPM)
-/* I2C5_SDA */
-/* I2C5_SCL */
-#endif
-/* Ensure UART pins are in native mode for H1. */
-/* UART0_RXD */		/* UART_PCH_RX_DEBUG_TX */
-/* UART0_TXD */		/* UART_PCH_RX_DEBUG_RX */
-/* UART1_RXD */         PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_SINGLE,
-					 INVERT), /* H1_PCH_INT_ODL */
-};
-
-const struct pad_config *__weak variant_gpio_table(size_t *num)
-{
-	*num = ARRAY_SIZE(gpio_table);
-	return gpio_table;
-}
-
-const struct pad_config *__weak
-	variant_early_gpio_table(size_t *num)
-{
-	*num = ARRAY_SIZE(early_gpio_table);
-	return early_gpio_table;
-}
-
-static const struct cros_gpio cros_gpios[] = {
-	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
-};
-
-const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
-{
-	*num = ARRAY_SIZE(cros_gpios);
-	return cros_gpios;
-}
diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/acpi/dptf.asl
deleted file mode 100644
index aba1385d80..0000000000
--- a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/acpi/dptf.asl
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2017 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define DPTF_CPU_PASSIVE	95
-#define DPTF_CPU_CRITICAL	105
-#define DPTF_CPU_ACTIVE_AC0	90
-#define DPTF_CPU_ACTIVE_AC1	80
-#define DPTF_CPU_ACTIVE_AC2	70
-#define DPTF_CPU_ACTIVE_AC3	60
-#define DPTF_CPU_ACTIVE_AC4	50
-
-#define DPTF_TSR0_SENSOR_ID	0
-#define DPTF_TSR0_SENSOR_NAME	"Battery"
-#define DPTF_TSR0_PASSIVE	120
-#define DPTF_TSR0_CRITICAL	125
-
-#define DPTF_TSR1_SENSOR_ID	1
-#define DPTF_TSR1_SENSOR_NAME	"Ambient"
-#define DPTF_TSR1_PASSIVE	46
-#define DPTF_TSR1_CRITICAL	75
-
-#define DPTF_TSR2_SENSOR_ID	2
-#define DPTF_TSR2_SENSOR_NAME	"Charger"
-#define DPTF_TSR2_PASSIVE	58
-#define DPTF_TSR2_CRITICAL	90
-
-#define DPTF_ENABLE_CHARGER
-
-/* Charger performance states, board-specific values from charger and EC */
-Name (CHPS, Package () {
-	Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 },	/* 3A (MAX) */
-	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
-	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
-	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
-	Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 },	/* 0.0A */
-})
-
-Name (DTRT, Package () {
-	/* CPU Throttle Effect on CPU */
-	Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 },
-
-	/* CPU Effect on Temp Sensor 0 */
-	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 },
-
-#ifdef DPTF_ENABLE_CHARGER
-	/* Charger Effect on Temp Sensor 2 */
-	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 },
-#endif
-
-	/* CPU Effect on Temp Sensor 1 */
-	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 },
-})
-
-Name (MPPC, Package ()
-{
-	0x2,		/* Revision */
-	Package () {	/* Power Limit 1 */
-		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
-		3000,	/* PowerLimitMinimum */
-		12000,	/* PowerLimitMaximum */
-		1000,	/* TimeWindowMinimum */
-		1000,	/* TimeWindowMaximum */
-		200	/* StepSize */
-	},
-	Package () {	/* Power Limit 2 */
-		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
-		8000,	/* PowerLimitMinimum */
-		15000,	/* PowerLimitMaximum */
-		1000,	/* TimeWindowMinimum */
-		1000,	/* TimeWindowMaximum */
-		1000	/* StepSize */
-	}
-})
diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/ec.h
deleted file mode 100644
index 9766c1da36..0000000000
--- a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/ec.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __BASEBOARD_EC_H__
-#define __BASEBOARD_EC_H__
-
-#include <ec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-
-#include "gpio.h"
-
-#define MAINBOARD_EC_SCI_EVENTS \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)       |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
-
-#define MAINBOARD_EC_SMI_EVENTS \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
-
-/* EC can wake from S5 with lid or power button */
-#define MAINBOARD_EC_S5_WAKE_EVENTS \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
-
-/*
- * EC can wake from S3 with lid or power button or key press or
- * mode change event.
- */
-#define MAINBOARD_EC_S3_WAKE_EVENTS \
-	(MAINBOARD_EC_S5_WAKE_EVENTS |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
-
-/* Log EC wake events plus EC shutdown events */
-#define MAINBOARD_EC_LOG_EVENTS \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
-
-/*
- * ACPI related definitions for ASL code.
- */
-
-/* Enable EC backed ALS device in ACPI */
-#define EC_ENABLE_ALS_DEVICE
-
-/* Enable EC backed PD MCU device in ACPI */
-#define EC_ENABLE_PD_MCU_DEVICE
-
-/* Enable LID switch and provide wake pin for EC */
-#define EC_ENABLE_LID_SWITCH
-#define EC_ENABLE_WAKE_PIN	GPE_EC_WAKE
-
-#define SIO_EC_MEMMAP_ENABLE	/* EC Memory Map Resources */
-#define SIO_EC_HOST_ENABLE	/* EC Host Interface Resources */
-
-#define EC_ENABLE_MKBP_DEVICE	/* Enable cros_ec_keyb device */
-
-#endif
diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h
deleted file mode 100644
index f1460d2cbf..0000000000
--- a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
- * GNU General Public License for more details.
- */
-
-#ifndef __BASEBOARD_GPIO_H__
-#define __BASEBOARD_GPIO_H__
-
-#include <soc/gpe.h>
-#include <soc/gpio.h>
-
-/* Memory configuration board straps */
-#define GPIO_MEM_CONFIG_0	GPP_D3
-#define GPIO_MEM_CONFIG_1	GPP_D21
-#define GPIO_MEM_CONFIG_2	GPP_D22
-#define GPIO_MEM_CONFIG_3	GPP_D0
-
-/* EC in RW */
-#define GPIO_EC_IN_RW		GPP_A8
-
-/* BIOS Flash Write Protect */
-#define GPIO_PCH_WP		GPP_H12
-
-/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
-#define GPE_EC_WAKE		GPE0_LAN_WAK
-
-/* eSPI virtual wire reporting */
-#define EC_SCI_GPI		GPE0_ESPI
-#endif
diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h
deleted file mode 100644
index e8c7c20601..0000000000
--- a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2017 Google Inc.
- * Copyright 2017 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __BASEBOARD_VARIANTS_H__
-#define __BASEBOARD_VARIANTS_H__
-
-#include <soc/cnl_memcfg_init.h>
-#include <soc/gpio.h>
-#include <stdint.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-/* Return the board id for the current variant board. */
-int variant_board_id(void);
-
-/*
- * The next set of functions return the gpio table and fill in the number of
- * entries for each table.
- */
-const struct pad_config *variant_gpio_table(size_t *num);
-const struct pad_config *variant_early_gpio_table(size_t *num);
-
-const struct cros_gpio *variant_cros_gpios(size_t *num);
-
-/* Return LPDDR4 configuration structure. */
-const struct cnl_mb_cfg *variant_lpddr4_config(void);
-
-/* Return memory SKU for the board. */
-size_t variant_memory_sku(void);
-
-/* Seed the NHLT tables with the board specific information. */
-struct nhlt;
-void variant_nhlt_init(struct nhlt *nhlt);
-
-#endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/zoombini/variants/baseboard/nhlt.c b/src/mainboard/google/zoombini/variants/baseboard/nhlt.c
deleted file mode 100644
index 84c1ec5ddf..0000000000
--- a/src/mainboard/google/zoombini/variants/baseboard/nhlt.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2017 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <baseboard/variants.h>
-#include <console/console.h>
-#include <nhlt.h>
-#include <soc/nhlt.h>
-
-void __weak variant_nhlt_init(struct nhlt *nhlt)
-{
-	/* 1-dmic configuration */
-	if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) &&
-		!nhlt_soc_add_dmic_array(nhlt, 1))
-		printk(BIOS_DEBUG, "Added 1CH DMIC array.\n");
-	/* 2-dmic configuration */
-	if (IS_ENABLED(CONFIG_NHLT_DMIC_2CH_16B) &&
-		!nhlt_soc_add_dmic_array(nhlt, 2))
-		printk(BIOS_DEBUG, "Added 2CH DMIC array.\n");
-	/* 4-dmic configuration */
-	if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH_16B) &&
-		!nhlt_soc_add_dmic_array(nhlt, 4))
-		printk(BIOS_DEBUG, "Added 4CH DMIC array.\n");
-
-
-	if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98357_DA7219_NHLT)) {
-		/* Dialog for Headset codec. Headset codec is bi-directional
-		   but uses the same configuration settings for render and
-		   capture endpoints. */
-		if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP2))
-			printk(BIOS_DEBUG, "Added Dialog_7219 codec.\n");
-
-		/* MAXIM Smart Amps for left and right speakers. */
-		if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP1))
-			printk(BIOS_DEBUG, "Added Maxim_98357 codec.\n");
-	}
-
-	if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98373_NHLT) &&
-		!nhlt_soc_add_max98373(nhlt, AUDIO_LINK_SSP1))
-		printk(BIOS_DEBUG, "Added Maxim_98373 codec.\n");
-}
diff --git a/src/mainboard/google/zoombini/variants/meowth/Makefile.inc b/src/mainboard/google/zoombini/variants/meowth/Makefile.inc
deleted file mode 100644
index 38653f18f3..0000000000
--- a/src/mainboard/google/zoombini/variants/meowth/Makefile.inc
+++ /dev/null
@@ -1,25 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2018 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-SPD_SOURCES = Samsung_K4F8E304HB_1GB		# 0b000
-SPD_SOURCES += Hynix_H9HCNNN8KUMLHR_1GB		# 0b001
-SPD_SOURCES += Samsung_K4F6E3S4HM_2GB		# 0b010
-SPD_SOURCES += Hynix_H9HCNNNCPUMLHR_4GB		# 0b011
-
-bootblock-y += gpio.c
-
-romstage-y += memory.c
-
-ramstage-y += gpio.c
diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
deleted file mode 100644
index b014353e0b..0000000000
--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
+++ /dev/null
@@ -1,204 +0,0 @@
-chip soc/intel/cannonlake
-
-	# Deep Sx states
-	register "deep_s3_enable_ac" = "0"
-	register "deep_s3_enable_dc" = "0"
-	register "deep_s5_enable_ac" = "1"
-	register "deep_s5_enable_dc" = "1"
-
-	# Debug Option
-	register "DebugConsent" = "DebugConsent_Disabled"
-
-	# GPE configuration
-	# Note that GPE events called out in ASL code rely on this
-	# route. i.e. If this route changes then the affected GPE
-	# offset bits also need to be changed.
-	register "gpe0_dw0" = "PMC_GPP_A"
-	register "gpe0_dw1" = "PMC_GPP_B"
-	register "gpe0_dw2" = "PMC_GPP_C"
-
-	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
-	register "gen1_dec" = "0x00fc0801"
-	register "gen2_dec" = "0x000c0201"
-	# EC memory map range is 0x900-0x9ff
-	register "gen3_dec" = "0x00fc0901"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-
-	# FSP configuration
-	register "SaGv" = "SaGv_Enabled"
-	register "ScsEmmcHs400Enabled" = "1"
-
-	# Intel Common SoC Config
-	#+-------------------+---------------------------+
-	#| Field             |  Value                    |
-	#+-------------------+---------------------------+
-	#| GSPI0             | cr50 TPM. Early init is   |
-	#|                   | required to set up a BAR  |
-	#|                   | for TPM communication     |
-	#|                   | before memory is up       |
-	#| I2C0              | Touchscreen Digitizer     |
-	#+-------------------+---------------------------+
-	register "common_soc_config" = "{
-		.gspi[0] = {
-			.speed_mhz = 1,
-			.early_init = 1,
-		},
-		.i2c[0] = {
-			.speed = I2C_SPEED_FAST_PLUS,
-			.rise_time_ns = 98,
-			.fall_time_ns = 38,
-		},
-	}"
-
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)"
-	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC3)"
-	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-	register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-	register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-	register "usb2_ports[6]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-	register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-	register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-	register "usb2_ports[9]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)"
-
-	register "PchHdaDspEnable" = "1"
-	register "PchHdaAudioLinkSsp0" = "1"
-	register "PchHdaAudioLinkSsp1" = "1"
-
-	# Enable cpufreq
-	register "speed_shift_enable" = "1"
-
-	# Enable Root port 8 (PCIe port 9) for NVMe
-	register "PcieRpEnable[8]" = "1"
-	register "PcieClkSrcUsage[3]" = "8"
-	register "PcieClkSrcClkReq[3]" = "3"
-
-	# Enable S0ix
-	register "s0ix_enable" = "1"
-
-	device domain 0 on
-		device pci 00.0 on  end # Host Bridge
-		device pci 02.0 on  end # Integrated Graphics Device
-		device pci 04.0 on  end # SA Thermal device
-		device pci 12.0 on  end # Thermal Subsystem
-		device pci 12.5 off end # UFS SCS
-		device pci 12.6 off end # GSPI #2
-		device pci 14.0 on  end # USB xHCI
-		device pci 14.1 off end # USB xDCI (OTG)
-		chip drivers/intel/wifi
-			register "wake" = "PME_B0_EN_BIT"
-			device pci 14.3 on  end # CNVi wifi
-		end
-		device pci 14.5 off end # SDCard
-		device pci 15.0 on
-			chip drivers/i2c/hid
-				register "generic.hid" = ""WCOM50C1""
-				register "generic.desc" = ""WCOM Digitizer""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C14_IRQ)"
-				register "generic.speed" = "I2C_SPEED_FAST_PLUS"
-				register "hid_desc_reg_offset" = "0x1"
-				device i2c 0a on end
-			end
-		end # I2C #0
-		device pci 15.1 on
-			chip drivers/i2c/generic
-				register "hid" = ""STH9310""
-				register "name" = ""SEMTECH SX9310""
-				register "desc" = ""Left SAR Proximity Sensor""
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C3_IRQ)"
-				register "speed" = "I2C_SPEED_FAST_PLUS"
-				register "uid" = "1"
-				device i2c 28 on end
-			end
-		end # I2C #1
-		device pci 15.2 on end # I2C #2
-		device pci 15.3 on
-			chip drivers/i2c/max98373
-				register "vmon_slot_no" = "4"
-				register "imon_slot_no" = "5"
-				register "uid" = "0"
-				register "desc" = ""RIGHT SPEAKER AMP""
-				register "name" = ""MAXR""
-				device i2c 31 on end
-			end
-			chip drivers/i2c/max98373
-				register "vmon_slot_no" = "6"
-				register "imon_slot_no" = "7"
-				register "uid" = "1"
-				register "desc" = ""LEFT SPEAKER AMP""
-				register "name" = ""MAXL""
-				device i2c 32 on end
-			end
-		end # I2C #3
-		device pci 16.0 on  end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT Redirection
-		device pci 16.4 off end # Management Engine Interface 3
-		device pci 16.5 off end # Management Engine Interface 4
-		device pci 17.0 off end # SATA
-		device pci 19.0 on  end # I2C #4
-		device pci 19.1 on
-			chip drivers/i2c/generic
-				register "hid" = ""STH9310""
-				register "name" = ""SEMTECH SX9310""
-				register "desc" = ""Right SAR Proximity Sensor""
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C4_IRQ)"
-				register "speed" = "I2C_SPEED_FAST_PLUS"
-				register "uid" = "0"
-				device i2c 28 on end
-			end
-		end # I2C #5
-		device pci 19.2 on  end # UART #2
-		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on end # PCI Express Port 9
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 off end # PCI Express Port 13
-		device pci 1d.5 off end # PCI Express Port 14
-		device pci 1d.6 off end # PCI Express Port 15
-		device pci 1d.7 off end # PCI Express Port 16
-		device pci 1e.0 on  end # UART #0
-		device pci 1e.1 off end # UART #1
-		device pci 1e.2 on
-			chip drivers/spi/acpi
-				register "hid" = "ACPI_DT_NAMESPACE_HID"
-				register "compat_string" = ""google,cr50""
-				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C12_IRQ)"
-				device spi 0 on end
-			end
-		end # GSPI #0
-		device pci 1e.3 on
-			chip drivers/spi/acpi
-				register "hid" = "ACPI_DT_NAMESPACE_HID"
-				register "uid" = "1"
-				register "compat_string" = ""google,cros-ec-spi""
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A22_IRQ)"
-				device spi 0 on end
-			end
-		end # GSPI #1
-		device pci 1f.0 on
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end # LPC Interface
-		device pci 1f.1 on  end # P2SB
-		device pci 1f.2 on  end # Power Management Controller
-		device pci 1f.3 on  end # Intel HDA
-		device pci 1f.4 on  end # SMBus
-		device pci 1f.5 on  end # PCH SPI
-		device pci 1f.6 off end # GbE
-	end
-end
diff --git a/src/mainboard/google/zoombini/variants/meowth/gpio.c b/src/mainboard/google/zoombini/variants/meowth/gpio.c
deleted file mode 100644
index 0f356e4775..0000000000
--- a/src/mainboard/google/zoombini/variants/meowth/gpio.c
+++ /dev/null
@@ -1,289 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
- * GNU General Public License for more details.
- */
-
-#include <baseboard/gpio.h>
-#include <baseboard/variants.h>
-
-/* Pad configuration in ramstage */
-static const struct pad_config gpio_table[] = {
-/* RCIN# */		PAD_NC(GPP_A0, NONE), /* PCH_CSI_GPIO1 */
-/* ESPI_IO0 */		PAD_CFG_NF(GPP_A1, NONE, DEEP, NF2), /* ESPI_IO0_R */
-/* ESPI_IO1 */		PAD_CFG_NF(GPP_A2, NONE, DEEP, NF2), /* ESPI_IO0_R */
-/* ESPI_IO2 */		PAD_CFG_NF(GPP_A3, NONE, DEEP, NF2), /* ESPI_IO2_R */
-/* ESPI_IO3 */		PAD_CFG_NF(GPP_A4, NONE, DEEP, NF2), /* ESPI_IO3_R */
-/* ESPI_CS# */		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF2), /* ESPI_CS_L */
-/* SERIRQ */		PAD_NC(GPP_A6, NONE),
-/* PIRQA# */		PAD_NC(GPP_A7, NONE),
-/* CLKRUN# */		PAD_CFG_GPI(GPP_A8, NONE, DEEP), /* EC_IN_RW_OD */
-/* ESPI_CLK */		PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2), /* ESPI_CLK_R */
-/* CLKOUT_LPC1 */	PAD_NC(GPP_A10, NONE),
-/* PME# */		PAD_CFG_GPO(GPP_A11, 1, DEEP), /* PCH_FP_PWR_EN */
-/* BM_BUSY# */		PAD_CFG_GPI(GPP_A12, NONE, DEEP), /* FPMCU_INT */
-/* SUSWARN# */		PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUSWARN_L */
-/* ESPI_RESET# */	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF2), /* ESPI_RESET_L */
-/* SUSACK# */		PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SUSACK_L */
-/* SD_1P8_SEL */	PAD_NC(GPP_A16, NONE),
-/* SD_PWR_EN# */	PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
-/* ISH_GP0 */		PAD_NC(GPP_A18, NONE),
-/* ISH_GP1 */		PAD_NC(GPP_A19, NONE),
-/* ISH_GP2 */		PAD_NC(GPP_A20, NONE),
-/* ISH_GP3 */		PAD_CFG_GPO(GPP_A21, 0, DEEP), /* PCH_FPMCU_BOOT0 */
-/* ISH_GP4 */		PAD_CFG_GPI_APIC(GPP_A22, NONE, DEEP, LEVEL,
-					 NONE), /* FPMCU_INT */
-/* ISH_GP5 */		PAD_CFG_GPO(GPP_A23, 1, DEEP), /* PCH_FPMCU_RST_ODL */
-/* CORE_VID0 */		PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */
-/* CORE_VID1 */		PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */
-/* VRALERT# */		PAD_NC(GPP_B2, NONE),
-/* CPU_GP2 */		PAD_NC(GPP_B3, NONE),
-/* CPU_GP3 */		PAD_NC(GPP_B4, NONE),
-/* SRCCLKREQ0# */	PAD_NC(GPP_B5, NONE),
-/* SRCCLKREQ1# */	PAD_NC(GPP_B6, NONE),
-/* SRCCLKREQ2# */	PAD_NC(GPP_B7, NONE),
-/* SRCCLKREQ3# */	PAD_CFG_NF(GPP_B8, NONE, DEEP,
-				   NF1), /* PCIE_NVME_CLKREQ_ODL */
-/* SRCCLKREQ4# */	PAD_NC(GPP_B9, NONE),
-/* SRCCLKREQ5# */	PAD_NC(GPP_B10, NONE),
-/* EXT_PWR_GATE# */
-/* SLP_S0# */		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_SO_L */
-/* PLTRST# */		PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLT_RST_L */
-/* SPKR */		PAD_CFG_GPI(GPP_B14, NONE, DEEP), /* GPP_B14_STRAP */
-#if IS_ENABLED(CONFIG_ZOOMBINI_USE_SPI_TPM)
-/* GSPI0_CS# */		PAD_CFG_NF(GPP_B15, NONE, DEEP,
-				   NF1), /* H1_SLAVE_SPI_CS_L */
-/* GSPI0_CLK */		PAD_CFG_NF(GPP_B16, NONE, DEEP,
-				   NF1), /* H1_SLAVE_SPI_CLK */
-/* GSPI0_MISO */	PAD_CFG_NF(GPP_B17, NONE, DEEP,
-				   NF1), /* H1_SLAVE_SPI_MISO_R */
-/* GSPI0_MOSI */	PAD_CFG_NF(GPP_B18, NONE, DEEP,
-				   NF1), /* H1_SLAVE_SPI_MOSI_R */
-#else
-/* GSPI0_CS# */		PAD_NC(GPP_B15, NONE),
-/* GSPI0_CLK */		PAD_NC(GPP_B16, NONE),
-/* GSPI0_MISO */	PAD_NC(GPP_B17, NONE),
-/* GSPI0_MOSI */	PAD_NC(GPP_B18, NONE),
-#endif
-/* GSPI1_CS# */		PAD_CFG_NF(GPP_B19, NONE, DEEP,
-				   NF1), /* PCH_FPMCU_SPI_CS_L */
-/* GSPI1_CLK */		PAD_CFG_NF(GPP_B20, NONE, DEEP,
-				   NF1), /* PCH_FPMCU_SPI_CLK */
-/* GSPI1_MISO */	PAD_CFG_NF(GPP_B21, NONE, DEEP,
-				   NF1), /* PCH_FPMCU_SPI_MISO_R */
-/* GSPI1_MOSI */	PAD_CFG_NF(GPP_B22, NONE, DEEP,
-				   NF1), /* PCH_FPMCU_SPI_MOSI_R */
-/* SML1ALERT# */	PAD_CFG_GPI(GPP_B23, NONE, DEEP), /* GPP_B23_STRAP */
-/* SMBCLK */		PAD_NC(GPP_C0, NONE),
-/* SMBDATA */		PAD_NC(GPP_C1, NONE),
-/* SMBALERT# */		PAD_CFG_GPI(GPP_C2, NONE, DEEP), /* GPP_C2_STRAP */
-/* SML0CLK */		PAD_CFG_GPI_APIC(GPP_C3, NONE, DEEP, LEVEL,
-					NONE), /* PCH_SAR1_INT_L */
-/* SML0DATA */		PAD_CFG_GPI_APIC(GPP_C4, NONE, DEEP, LEVEL,
-					NONE), /* PCH_SAR0_INT_L */
-/* SML0ALERT# */	PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* GPP_C5_STRAP */
-/* SM1CLK */		PAD_NC(GPP_C6, NONE),
-/* SM1DATA */		PAD_NC(GPP_C7, NONE),
-/* UART0_RXD */		PAD_CFG_NF(GPP_C8, NONE, DEEP,
-				   NF1), /* UART_PCH_RX_DEBUG_TX */
-/* UART0_TXD */		PAD_CFG_NF(GPP_C9, NONE, DEEP,
-				   NF1), /* UART_PCH_TX_DEBUG_RX */
-/* UART0_RTS# */	PAD_CFG_GPO(GPP_C10, 1, DEEP), /* PP3300_TOUCH_EN */
-/* UART0_CTS# */	PAD_NC(GPP_C11, NONE),
-/* Only P0 boards need an internal pullup */
-/* UART1_RXD */         PAD_CFG_GPI_APIC(GPP_C12, UP_20K, DEEP, EDGE_SINGLE,
-					 INVERT), /* H1_PCH_INT_ODL */
-/* UART1_TXD */		PAD_NC(GPP_C13, NONE),
-/* UART1_RTS# */	PAD_CFG_GPI_APIC(GPP_C14, NONE, DEEP, LEVEL,
-					NONE), /* TOUCHSCREEN_INT_ODL */
-/* UART1_CTS# */	PAD_NC(GPP_C15, NONE),
-/* I2C0_SDA */		PAD_CFG_NF(GPP_C16, NONE, DEEP,
-				   NF1), /* PCH_TOUCHSCREEN_I2C0_SDA */
-/* I2C0_SCL */		PAD_CFG_NF(GPP_C17, NONE, DEEP,
-				   NF1), /* PCH_TOUCHSCREEN_I2C0_SCL */
-/* I2C1_SDA */		PAD_CFG_NF(GPP_C18, NONE, DEEP,
-				   NF1), /* PCH_DISPLAY_SAR1_I2C1_SDA */
-/* I2C1_SCL */		PAD_CFG_NF(GPP_C19, NONE, DEEP,
-				   NF1), /* PCH_DISPLAY_SAR1_I2C1_SCL */
-/* UART2_RXD */		PAD_NC(GPP_C20, NONE),
-/* UART2_TXD */		PAD_NC(GPP_C21, NONE),
-/* UART2_RTS# */	PAD_NC(GPP_C22, NONE),
-/* UART2_CTS# */	PAD_NC(GPP_C23, NONE),
-/* SPI1_CS# */		PAD_CFG_GPI(GPP_D0, NONE, DEEP), /* PCH_MEM_STRAP3 */
-/* SPI1_CLK */		PAD_NC(GPP_D1, NONE),
-/* SPI1_MISO */		PAD_NC(GPP_D2, NONE),
-/* SPI1_MOSI */		PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* PCH_MEM_STRAP0 */
-/* FASHTRIG */		PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), /* FCAM_MCLK */
-/* ISH_I2C0_SDA */	PAD_NC(GPP_D5, NONE),
-/* ISH_I2C0_SCL */	PAD_NC(GPP_D6, NONE),
-/* ISH_I2C1_SDA */	PAD_CFG_GPO(GPP_D7, 1, DEEP), /* FCAM_RST_L */
-/* ISH_I2C1_SCL */	PAD_CFG_GPO(GPP_D8, 1, DEEP), /* DMIC_PWR_EN */
-/* ISH_SPI_CS# */	PAD_NC(GPP_D9, NONE),
-/* ISH_SPI_CLK */	PAD_CFG_GPO(GPP_D10, 0, DEEP), /* FCAM_PWR_EN */
-/* ISH_SPI_MISO */	PAD_NC(GPP_D11, NONE),
-/* ISH_SPI_MOSI */	PAD_CFG_GPI(GPP_D12, NONE, DEEP), /* GPP_D12_STRAP */
-/* ISH_UART0_RXD */	PAD_NC(GPP_D13, NONE), /* ISH_UART_RX */
-/* ISH_UART0_TXD */	PAD_NC(GPP_D14, NONE), /* ISH_UART_TX */
-/* ISH_UART0_RTS# */	PAD_CFG_GPO(GPP_D15, 1, DEEP), /* TOUCHSCREEN_RST_ODL */
-/* ISH_UART0_CTS# */	PAD_CFG_GPO(GPP_D16, 1, DEEP), /* SPKR_HWRST_L */
-/* DMIC_CLK1 */		PAD_CFG_NF(GPP_D17, NONE, DEEP,
-				   NF1), /* DB0_PCH_DMIC_CLK_R */
-/* DMIC_DATA1 */	PAD_CFG_NF(GPP_D18, NONE, DEEP,
-				   NF1), /* DB0TX_PCHRX_DMIC_DATA */
-/* DMIC_CLK0 */		PAD_NC(GPP_D19, NONE),
-/* DMIC_DATA0 */	PAD_NC(GPP_D20, NONE),
-/* SPI1_IO2 */		PAD_CFG_GPI(GPP_D21, NONE, DEEP), /* PCH_MEM_STRAP1 */
-/* SPI1_IO3 */		PAD_CFG_GPI(GPP_D22, NONE, DEEP), /* PCH_MEM_STRAP2 */
-/* I2S_MCLK */
-/* SATAXPCI0 */		PAD_CFG_GPO(GPP_E0, 0, DEEP), /* RCAM_PWR_EN */
-/* SATAXPCIE1 */	PAD_CFG_GPO(GPP_E1, 1, DEEP), /* RCAM_RST_L */
-/* SATAXPCIE2 */	PAD_NC(GPP_E2, NONE),
-/* CPU_GP0 */		PAD_NC(GPP_E3, NONE),
-/* SATA_DEVSLP0 */	PAD_NC(GPP_E4, NONE),
-/* SATA_DEVSLP1 */	PAD_NC(GPP_E5, NONE),
-/* SATA_DEVSLP2 */	PAD_NC(GPP_E6, NONE),
-/* CPU_GP1 */		PAD_NC(GPP_E7, NONE),
-/* SATALED# */		PAD_NC(GPP_E8, NONE),
-/* USB2_OCO# */		PAD_NC(GPP_E9, NONE),
-/* USB2_OC1# */		PAD_NC(GPP_E10, NONE),
-/* USB2_OC2# */		PAD_CFG_NF(GPP_E11, NONE, DEEP,
-				   NF1), /* USB_C0_OC_ODL */
-/* USB2_OC3# */		PAD_CFG_NF(GPP_E12, NONE, DEEP,
-				   NF1), /* USB_C1_OC_ODL */
-/* DDPB_HPD0 */		PAD_CFG_NF(GPP_E13, NONE, DEEP,
-				   NF1), /* EC_USB_C0_HPD */
-/* DDPC_HPD1 */		PAD_CFG_NF(GPP_E14, NONE, DEEP,
-				   NF1), /* EC_USB_C1_HPD */
-/* DDPD_HPD2 */		PAD_CFG_NF(GPP_E15, NONE, DEEP,
-				   NF1), /* EC_USB_C2_HPD */
-/* DDPE_HPD3 */		PAD_NC(GPP_E16, NONE),
-/* EDP_HPD */
-/* DDPB_CTRLCLK */	PAD_NC(GPP_E18, NONE),
-/* DDPB_CTRLDATA */	PAD_CFG_GPI(GPP_E19, NONE, DEEP), /* GPP_E19_STRAP */
-/* DDPC_CTRLCLK */	PAD_NC(GPP_E20, NONE),
-/* DDPC_CTRLDATA */	PAD_CFG_GPI(GPP_E21, NONE, DEEP), /* GPP_E21_STRAP */
-/* DDPD_CTRLCLK */	PAD_NC(GPP_E22, NONE),
-/* DDPD_CTRLDATA */	PAD_CFG_GPI(GPP_E23, NONE, DEEP), /* GPP_E23_STRAP */
-/* I2S2_SFRM */		PAD_CFG_GPO(GPP_F1, 0, DEEP),
-					/* WWAN_RESET_1V8_ODL */
-/* I2S2_TXD */		PAD_NC(GPP_F2, NONE),
-/* I2S2_RXD */		PAD_NC(GPP_F3, NONE),
-/* I2C2_SDA */		PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_BRI_DT_R */
-/* I2C2_SCL */		PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* CNV_BRI_RSP */
-/* I2C3_SDA */		PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* CNV_RGI_DT_R */
-/* I2C3_SCL */		PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* CNV_RGI_RSP */
-/* I2C4_SDA */		PAD_NC(GPP_F8, NONE),
-/* I2C4_SCL */		PAD_NC(GPP_F9, NONE),
-/* I2C5_SDA */		PAD_CFG_GPI(GPP_F10, NONE,
-				    DEEP), /* OPVR_MCIVR_BREAK_L */
-/* I2C5_SCL */		PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), /* EMMC_CMD */
-/* EMMC_CMD */		PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DAT0 */
-/* EMMC_DATA0 */	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DAT1 */
-/* EMMC_DATA1 */	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), /* EMMC_DAT2 */
-/* EMMC_DATA2 */	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), /* EMMC_DAT3 */
-/* EMMC_DATA3 */	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* EMMC_DAT4 */
-/* EMMC_DATA4 */	PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), /* EMMC_DAT5 */
-/* EMMC_DATA5 */	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), /* EMMC_DAT6 */
-/* EMMC_DATA6 */	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* EMMC_DAT7 */
-/* EMMC_DATA7 */	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */
-/* EMMC_RCLK */		PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */
-/* EMMC_CLK */		PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* EMMC_RST_ODL */
-/* RSVD */
-/* SD_CMD */		PAD_NC(GPP_G0, NONE),
-/* SD_DATA0 */		PAD_NC(GPP_G1, NONE),
-/* SD_DATA1 */		PAD_NC(GPP_G2, NONE),
-/* SD_DATA2 */		PAD_NC(GPP_G3, NONE),
-/* SD_DATA3 */		PAD_NC(GPP_G4, NONE),
-/* SD_CD# */		PAD_NC(GPP_G5, NONE),
-/* SD_CLK */		PAD_NC(GPP_G6, NONE),
-/* SD_WP */		PAD_NC(GPP_G7, NONE),
-/* I2S2_SCLK */		PAD_NC(GPP_H0, NONE),
-/* I2S2_SFRM */		PAD_CFG_NF(GPP_H1, NONE, DEEP,
-				   NF3), /* CNV_RF_RESET_L */
-/* I2S2_TXD */		PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* WLAN_CLKREQ0 */
-/* I2S2_RXD */		PAD_NC(GPP_H3, NONE),
-/* I2C2_SDA */		PAD_NC(GPP_H4, NONE),
-/* I2C2_SCL */		PAD_NC(GPP_H5, NONE),
-/* I2C3_SDA */		PAD_CFG_NF(GPP_H6, NONE, DEEP,
-				   NF1), /* PCH_AUDIO_I2C3_SDA */
-/* I2C3_SCL */		PAD_CFG_NF(GPP_H7, NONE, DEEP,
-				   NF1), /* PCH_AUDIO_I2C3_SCL */
-/* I2C4_SDA */		PAD_CFG_NF(GPP_H8, NONE, DEEP,
-				   NF1), /* PCH_FCAM_I2C4_SDA */
-/* I2C4_SCL */		PAD_CFG_NF(GPP_H9, NONE, DEEP,
-				   NF1), /* PCH_FCAM_I2C4_SCL */
-/* I2C5_SDA */		PAD_CFG_NF(GPP_H10, NONE, DEEP,
-				   NF1), /* PCH_RCAM_SAR0_I2C5_SDA */
-/* I2C5_SCL */		PAD_CFG_NF(GPP_H11, NONE, DEEP,
-				   NF1), /* PCH_RCAM_SAR0_I2C5_SCL */
-/* M2_SKT2_CFG0 */	PAD_CFG_GPI(GPP_H12, NONE, DEEP), /* PCH_WP_OD */
-/* M2_SKT2_CFG1 */	PAD_NC(GPP_H13, NONE),
-/* M2_SKT2_CFG2 */	PAD_NC(GPP_H14, NONE),
-/* M2_SKT2_CFG3 */	PAD_NC(GPP_H15, NONE),
-/* DDPF_CTRLCLK */
-/* DPPF_CTRLDATA */
-/* CPU_C10_GATE# */	PAD_CFG_NF(GPP_H18, NONE, DEEP,
-				   NF1), /* CPU_C10_GATE_PCH_L */
-/* TIMESYNC0 */		PAD_NC(GPP_H19, NONE),
-/* IMGCLKOUT1 */	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), /* RCAM_MCLK */
-/* GPP_H21 */		PAD_CFG_GPI(GPP_H21, NONE, DEEP), /* H21_STRAP */
-/* GPP_H22 */		PAD_NC(GPP_H22, NONE),
-/* GPP_H23 */		PAD_CFG_GPI(GPP_H23, NONE, DEEP), /* GPP_H23 */
-
-/* BATLOW# */		PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW_L */
-/* ACPRESENT */		PAD_NC(GPD1, NONE),
-/* LAN_WAKE# */		PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_ODL */
-/* PWRBTN# */		PAD_CFG_NF(GPD3, NONE, DEEP,
-				   NF1), /* EC_PCH_PWR_BTN_ODL */
-/* SLP_S3# */		PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S3_L */
-/* SLP_S4# */		PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SLP_S4_L */
-/* SLP_A# */		PAD_NC(GPD6, NONE),
-/* RSVD */		PAD_CFG_GPI(GPD7, NONE, DEEP), /* DPD7_Strap */
-/* SUSCLK */		PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* PCH_SUSCLK */
-/* SLP_WLAN# */		PAD_NC(GPD9, NONE),
-/* SLP_S5# */		PAD_NC(GPD10, NONE),
-/* LANPHYC */		PAD_NC(GPD11, NONE),
-};
-
-/* Early pad configuration in bootblock */
-static const struct pad_config early_gpio_table[] = {
-#if IS_ENABLED(CONFIG_ZOOMBINI_USE_SPI_TPM)
-/* GSPI0_CS# */		PAD_CFG_NF(GPP_B15, NONE, DEEP,
-				   NF1), /* PCH_SPI_H1_3V3_CS_L */
-/* GSPI0_CLK */		PAD_CFG_NF(GPP_B16, NONE, DEEP,
-				   NF1), /* PCH_SPI_H1_3V3_CLK */
-/* GSPI0_MISO */	PAD_CFG_NF(GPP_B17, NONE, DEEP,
-				   NF1), /* PCH_SPI_H1_3V3_MISO */
-/* GSPI0_MOSI */	PAD_CFG_NF(GPP_B18, NONE, DEEP,
-				   NF1), /* PCH_SPI_H1_3V3_MOSI */
-#else
-/* GSPI0_CS# */		PAD_NC(GPP_B15, NONE),
-/* GSPI0_CLK */		PAD_NC(GPP_B16, NONE),
-/* GSPI0_MISO */	PAD_NC(GPP_B17, NONE),
-/* GSPI0_MOSI */	PAD_NC(GPP_B18, NONE),
-#endif
-/* Only P0 boards need an internal pullup */
-/* UART1_RXD */         PAD_CFG_GPI_APIC(GPP_C12, UP_20K, DEEP, EDGE_SINGLE,
-					 INVERT), /* H1_PCH_INT_ODL */
-};
-
-const struct pad_config *variant_gpio_table(size_t *num)
-{
-	*num = ARRAY_SIZE(gpio_table);
-	return gpio_table;
-}
-
-const struct pad_config *variant_early_gpio_table(size_t *num)
-{
-	*num = ARRAY_SIZE(early_gpio_table);
-	return early_gpio_table;
-}
diff --git a/src/mainboard/google/zoombini/variants/meowth/include/variant/acpi/dptf.asl b/src/mainboard/google/zoombini/variants/meowth/include/variant/acpi/dptf.asl
deleted file mode 100644
index a9ec74269f..0000000000
--- a/src/mainboard/google/zoombini/variants/meowth/include/variant/acpi/dptf.asl
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <baseboard/acpi/dptf.asl>
diff --git a/src/mainboard/google/zoombini/variants/meowth/include/variant/ec.h b/src/mainboard/google/zoombini/variants/meowth/include/variant/ec.h
deleted file mode 100644
index ef47d3751c..0000000000
--- a/src/mainboard/google/zoombini/variants/meowth/include/variant/ec.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MAINBOARD_EC_H__
-#define __MAINBOARD_EC_H__
-
-#include <baseboard/ec.h>
-
-#endif /* __MAINBOARD_EC_H__ */
diff --git a/src/mainboard/google/zoombini/variants/meowth/include/variant/gpio.h b/src/mainboard/google/zoombini/variants/meowth/include/variant/gpio.h
deleted file mode 100644
index 136e11b595..0000000000
--- a/src/mainboard/google/zoombini/variants/meowth/include/variant/gpio.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MAINBOARD_GPIO_H__
-#define __MAINBOARD_GPIO_H__
-
-#include <baseboard/gpio.h>
-
-#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/zoombini/variants/meowth/memory.c b/src/mainboard/google/zoombini/variants/meowth/memory.c
deleted file mode 100644
index 02c9ab9048..0000000000
--- a/src/mainboard/google/zoombini/variants/meowth/memory.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <baseboard/variants.h>
-#include <baseboard/gpio.h>
-#include <gpio.h>
-#include <soc/cnl_memcfg_init.h>
-
-static const struct cnl_mb_cfg meowth_lpddr4_cfg = {
-	.dq_map[DDR_CH0] = {
-		/*
-		 * CLK0 goes to package 0 - Bytes[3:0],
-		 * CLK1 goes to package 1 - Bytes[7:4]
-		 */
-		{ 0x0F, 0xF0 },
-
-		/*
-		 * Cmd CAA goes to Bytes[3:0],
-		 * Cmd CAB goes to Bytes[7:4]
-		 */
-		{ 0x0F, 0xF0 },
-
-		/* CTL (CS) goes to all bytes */
-		{ 0xFF, 0x00 },
-	},
-
-	.dq_map[DDR_CH1] = {
-		/*
-		 * CLK0 goes to package 0 - Bytes[3:0],
-		 * CLK1 goes to package 1 - Bytes[7:4]
-		 */
-		{ 0x0F, 0xF0 },
-
-		/*
-		 * Cmd CAA goes to Bytes[3:0],
-		 * Cmd CAB goes to Bytes[7:4]
-		 */
-		{ 0x0F, 0xF0 },
-
-		/* CTL (CS) goes to all bytes */
-		{ 0xFF, 0x00 },
-	},
-
-	/*
-	 * The dqs_map arrays map the lpddr4 pins to the SoC pins
-	 * for both channels.
-	 *
-	 * On Intel's memory spreadsheet, enter the following:
-	 *
-	 * the index = dqs pin/set number on lpddr4 part
-	 * the value = dqs pin/set number on SoC
-	 *
-	 * and it will translate that and display 8 values per channel.
-	 * Those values are copied into the dqs_map arrays below.
-	 */
-	.dqs_map[DDR_CH0] = { 3, 1, 2, 0, 7, 5, 6, 4 },
-	.dqs_map[DDR_CH1] = { 2, 3, 1, 0, 7, 5, 6, 4 },
-
-	/* Meowth uses three 100 Ohm rcomp resistors */
-	.rcomp_resistor = { 100, 100, 100 },
-
-	/*
-	 * Meowth Rcomp target values.
-	 * Rcomp targets for zoombini should be
-	 * { 80, 40, 40, 40, 30 }, but we need to
-	 * nil out rcomp targets for now to avoid bug b:70896346
-	 */
-	.rcomp_targets = { 0, 0, 0, 0, 0 },
-
-	/* Meowth is a non-interleaved design */
-	.dq_pins_interleaved = 0,
-
-	/* Enable Early Command Training */
-	.ect = 1,
-};
-
-const struct cnl_mb_cfg *variant_lpddr4_config(void)
-{
-	return &meowth_lpddr4_cfg;
-}
diff --git a/src/mainboard/google/zoombini/variants/zoombini/Makefile.inc b/src/mainboard/google/zoombini/variants/zoombini/Makefile.inc
deleted file mode 100644
index bfa1848ba1..0000000000
--- a/src/mainboard/google/zoombini/variants/zoombini/Makefile.inc
+++ /dev/null
@@ -1,18 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2018 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-SPD_SOURCES = Hynix_H9HCNNN8KUMLHR_1GB          # 0b000
-SPD_SOURCES += Micron_MT53B512M32D2_2GB         # 0b001
-SPD_SOURCES += Micron_MT53B1024M32D4_4GB        # 0b010
diff --git a/src/mainboard/google/zoombini/variants/zoombini/include/variant/acpi/dptf.asl b/src/mainboard/google/zoombini/variants/zoombini/include/variant/acpi/dptf.asl
deleted file mode 100644
index 15c46e4bd8..0000000000
--- a/src/mainboard/google/zoombini/variants/zoombini/include/variant/acpi/dptf.asl
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <baseboard/acpi/dptf.asl>
diff --git a/src/mainboard/google/zoombini/variants/zoombini/include/variant/ec.h b/src/mainboard/google/zoombini/variants/zoombini/include/variant/ec.h
deleted file mode 100644
index ef47d3751c..0000000000
--- a/src/mainboard/google/zoombini/variants/zoombini/include/variant/ec.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MAINBOARD_EC_H__
-#define __MAINBOARD_EC_H__
-
-#include <baseboard/ec.h>
-
-#endif /* __MAINBOARD_EC_H__ */
diff --git a/src/mainboard/google/zoombini/variants/zoombini/include/variant/gpio.h b/src/mainboard/google/zoombini/variants/zoombini/include/variant/gpio.h
deleted file mode 100644
index 4f79495e4f..0000000000
--- a/src/mainboard/google/zoombini/variants/zoombini/include/variant/gpio.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MAINBOARD_GPIO_H__
-#define __MAINBOARD_GPIO_H__
-
-#include <baseboard/gpio.h>
-
-#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/util/release/genrelnotes b/util/release/genrelnotes
index 42848a18a2..0cc8b08308 100755
--- a/util/release/genrelnotes
+++ b/util/release/genrelnotes
@@ -313,7 +313,6 @@ get_log_dedupe "Google Reef / Pyro / Sand / Snappy / Nasher" "src/mainboard/goog
 get_log_dedupe "Siemens mc_apl1" "src/mainboard/siemens/mc_apl1" "mc_apl1"
 get_log_dedupe "Intel Apollolake" "src/soc/intel/apollolake" "apollolake\|apollo.lake"
 
-get_log_dedupe "Google Zoombini / Intel cannonlake_rvp" "src/mainboard/google/zoombini src/mainboard/intel/cannonlake_rvp" "zoombini\|cannonlake_rvp"
 get_log_dedupe "Intel CannonLake" "src/soc/intel/cannonlake src/mainboard/intel/cannonlake_rvp" "cannonlake"
 
 get_log_dedupe "Intel Galileo" "src/mainboard/intel/galileo" "galileo"