diff --git a/src/lib/Kconfig.cbfs_verification b/src/lib/Kconfig.cbfs_verification
index 33e5458650..9a9ba3189d 100644
--- a/src/lib/Kconfig.cbfs_verification
+++ b/src/lib/Kconfig.cbfs_verification
@@ -13,7 +13,7 @@ config CBFS_VERIFICATION
 	  file as it gets loaded by chaining it to a trust anchor that is
 	  embedded in the bootblock. This only makes sense if you use some
 	  out-of-band mechanism to guarantee the integrity of the bootblock
-	  itself, such as Intel BootGuard or flash write-protection.
+	  itself, such as Intel Boot Guard or flash write-protection.
 
 	  If a CBFS image was created with this option enabled, cbfstool will
 	  automatically update the hash embedded in the bootblock whenever it
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 9ead46bc98..fd5ffd9579 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -247,7 +247,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
 
 	/*
 	 * DMA Protected Range can be reserved below TSEG for PCODE patch
-	 * or TXT/BootGuard related data.  Rather than report a base address,
+	 * or TXT/Boot Guard related data.  Rather than report a base address,
 	 * the DPR register reports the TOP of the region, which is the same
 	 * as TSEG base. The region size is reported in MiB in bits 11:4.
 	 */
diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c
index 76ea35f87a..4511c07502 100644
--- a/src/soc/intel/broadwell/northbridge.c
+++ b/src/soc/intel/broadwell/northbridge.c
@@ -272,7 +272,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
 
 	/*
 	 * DMA Protected Range can be reserved below TSEG for PCODE patch
-	 * or TXT/BootGuard related data.  Rather than report a base address
+	 * or TXT/Boot Guard related data.  Rather than report a base address
 	 * the DPR register reports the TOP of the region, which is the same
 	 * as TSEG base.  The region size is reported in MiB in bits 11:4.
 	 */
diff --git a/util/intelmetool/intelmetool.c b/util/intelmetool/intelmetool.c
index 9105d3b82b..4216189e0e 100644
--- a/util/intelmetool/intelmetool.c
+++ b/util/intelmetool/intelmetool.c
@@ -346,7 +346,7 @@ static void dump_bootguard_info(void)
 	if (ME_major_ver &&
 	    (ME_major_ver < 9 ||
 	     (ME_major_ver == 9 && ME_minor_ver < 5))) {
-		printf(CGRN "Your system isn't BootGuard ready.\n"
+		printf(CGRN "Your system isn't Boot Guard ready.\n"
 		       "You can flash other firmware!\n" RESET);
 		rehide_me();
 		return;
@@ -354,7 +354,7 @@ static void dump_bootguard_info(void)
 
 	if (pci_read_long(dev, 0x40) & 0x10)
 		printf(CYEL "Your southbridge configuration is insecure!!\n"
-		       "BootGuard keys can be overwritten or wiped, or you are "
+		       "Boot Guard keys can be overwritten or wiped, or you are "
 		       "in developer mode.\n"
 		       RESET);
 	rehide_me();
@@ -380,10 +380,10 @@ static void dump_bootguard_info(void)
 		return;
 	}
 
-	printf("BootGuard MSR Output : 0x%" PRIx64 "\n", btg.raw);
+	printf("Boot Guard MSR Output : 0x%" PRIx64 "\n", btg.raw);
 
 	if (!btg.btg_capability) {
-		printf(CGRN "Your system isn't BootGuard ready.\n"
+		printf(CGRN "Your system isn't Boot Guard ready.\n"
 		       "You can flash other firmware!\n" RESET);
 		return;
 	}
@@ -412,7 +412,7 @@ static void dump_bootguard_info(void)
 			       "Cache-As-RAM.\nIt might be possible to flash other firmware.\n"
 			       RESET);
 	} else {
-		printf(CGRN "Your system is BootGuard ready but verified boot is disabled.\n"
+		printf(CGRN "Your system is Boot Guard ready but verified boot is disabled.\n"
 		       "You can flash other firmware!\n" RESET);
 	}
 }