nb/intel/sandybridge: Rename `read_training` function

Given that it sets the receive enable mode bit in the GDCRTRAININGMOD
register, it's clear that this is about receive enable calibration.

Remove a potentially-outdated comment. Proper documentation will be
written once code refactoring and various improvements are complete.

Change-Id: Iaefc8905adf2878bec3b43494dc53530064a9f5d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47576
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/northbridge/intel/sandybridge/raminit_common.c

@@ -1316,25 +1316,7 @@ static void compute_final_logic_delay(ramctr_timing *ctrl, int channel, int slot
 	printram("4028 -= %d;\n", logic_delay_min);
 }
 
-/*
- * Compensate the skew between DQS and DQs.
- *
- * To ease PCB design, a small skew between Data Strobe signals and Data Signals is allowed.
- * The controller has to measure and compensate this skew for every byte-lane. By delaying
- * either all DQ signals or DQS signal, a full phase shift can be introduced. It is assumed
- * that one byte-lane's DQs signals have the same routing delay.
- *
- * To measure the actual skew, the DRAM is placed in "read leveling" mode. In read leveling
- * mode the DRAM-chip outputs an alternating periodic pattern. The memory controller iterates
- * over all possible values to do a full phase shift and issues read commands. With DQS and
- * DQ in phase the data being read is expected to alternate on every byte:
- *
- *   0xFF 0x00 0xFF ...
- *
- * Once the controller has detected this pattern a bit in the result register is set for the
- * current phase shift.
- */
-int read_training(ramctr_timing *ctrl)
+int receive_enable_calibration(ramctr_timing *ctrl)
 {
 	int channel, slotrank, lane;
 	int err;

src/northbridge/intel/sandybridge/raminit_common.h

@@ -400,7 +400,7 @@ void dram_dimm_set_mapping(ramctr_timing *ctrl, int training);
 void dram_zones(ramctr_timing *ctrl, int training);
 void dram_memorymap(ramctr_timing *ctrl, int me_uma_size);
 void dram_jedecreset(ramctr_timing *ctrl);
-int read_training(ramctr_timing *ctrl);
+int receive_enable_calibration(ramctr_timing *ctrl);
 int write_training(ramctr_timing *ctrl);
 int command_training(ramctr_timing *ctrl);
 int read_mpr_training(ramctr_timing *ctrl);

src/northbridge/intel/sandybridge/raminit_native.c

@@ -680,7 +680,7 @@ int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_
 		/* Prepare for memory training */
 		prepare_training(ctrl);
 
-		err = read_training(ctrl);
+		err = receive_enable_calibration(ctrl);
 		if (err)
 			return err;