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intel/bd82x6x: Use generated ACPI PIRQ 

Enable change Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0
(sb/intel/common: Automatically generate ACPI PIRQ) for BD82X6X.

This generates the main ACPI _PRT table automatically based on the
chipset registers.

Tested on Intel NUC DCP847SKE with Linux 4.13.14:
$ cat /proc/interrupts
           CPU0       CPU1
  0:         23          0   IO-APIC   2-edge      timer
  8:          1          0   IO-APIC   8-edge      rtc0
  9:          0          0   IO-APIC   9-fasteoi   acpi
 19:         86          0   IO-APIC  19-fasteoi   ehci_hcd:usb1
 23:          0          0   IO-APIC  23-fasteoi   i801_smbus
[...MSI and other interrupts skipped...]

Log messages:
ACPI_PIRQ_GEN PCI: 00:02.0: pin=1 pirq=1
ACPI_PIRQ_GEN PCI: 00:1b.0: pin=1 pirq=1
ACPI_PIRQ_GEN PCI: 00:1c.0: pin=1 pirq=2
ACPI_PIRQ_GEN PCI: 00:1c.1: pin=2 pirq=6
ACPI_PIRQ_GEN PCI: 00:1c.2: pin=3 pirq=4
ACPI_PIRQ_GEN PCI: 00:1d.0: pin=1 pirq=4
ACPI_PIRQ_GEN PCI: 00:1f.2: pin=1 pirq=2
ACPI_PIRQ_GEN PCI: 00:1f.3: pin=2 pirq=8
ACPI_PIRQ_GEN PCI: 00:04.0: pin=1 pirq=1

Generated _PRT:
    Scope (\_SB.PCI0)
    {
        Method (_PRT, 0, NotSerialized)  // _PRT: PCI Routing Table
        {
            If (PICM)
            {
                Return (Package (0x09)
                {
                    Package (0x04)
                    {
                        0x0002FFFF,
                        0x00000000,
                        0x00000000,
                        0x00000010
                    },

                    Package (0x04)
                    {
                        0x001BFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000010
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000011
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000001,
                        0x00000000,
                        0x00000015
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000002,
                        0x00000000,
                        0x00000013
                    },

                    Package (0x04)
                    {
                        0x001DFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000013
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000011
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000001,
                        0x00000000,
                        0x00000017
                    },

                    Package (0x04)
                    {
                        0x0004FFFF,
                        0x00000000,
                        0x00000000,
                        0x00000010
                    }
                })
            }
            Else
            {
                Return (Package (0x09)
                {
                    Package (0x04)
                    {
                        0x0002FFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKA,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001BFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKA,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKB,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000001,
                        \_SB.PCI0.LPCB.LNKF,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000002,
                        \_SB.PCI0.LPCB.LNKD,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001DFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKD,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKB,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000001,
                        \_SB.PCI0.LPCB.LNKH,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x0004FFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKA,
                        0x00000000
                    }
                })
            }
        }
    }

Change-Id: I832a86925283d61b64b8268246d9e6f11994c120
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Tobias Diedrich 2017-12-14 00:29:01 +01:00 committed by Martin Roth
parent 9d8be5a857
commit 7f5efd90e5
41 changed files with 3 additions and 493 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/apple/macbookair4_2/dsdt.asl
View File

@ -36,7 +36,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

1
src/mainboard/asrock/b75pro3-m/dsdt.asl
View File

@ -40,7 +40,6 @@ DefinitionBlock(
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include "acpi/pci.asl"
}
}

1
src/mainboard/compulab/intense_pc/dsdt.asl
View File

@ -40,7 +40,6 @@ DefinitionBlock(
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
}
}
}

1
src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
View File

@ -21,7 +21,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

1
src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
View File

@ -21,7 +21,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

60
src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl
View File

@ -1,60 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* This is board specific information: IRQ routing for Sandybridge */
// PCI Interrupt Routing
Method(_PRT)
{
If (PICM) {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI)
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI)
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB
Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF
Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF
// LPC devices 0:1f.0
Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI)
Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH
Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA
})
} Else {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
})
}
}

1
src/mainboard/google/butterfly/dsdt.asl
View File

@ -44,7 +44,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include "acpi/sandybridge_pci_irqs.asl"
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

64
src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl
View File

@ -1,64 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* This is board specific information: IRQ routing for Sandybridge */
// PCI Interrupt Routing
Method(_PRT)
{
If (PICM) {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, 0, 16 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, 0, 16 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, 0, 19 },
Package() { 0x001cffff, 1, 0, 20 },
Package() { 0x001cffff, 2, 0, 17 },
Package() { 0x001cffff, 3, 0, 18 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, 0, 19 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, 0, 21 },
// LPC devices 0:1f.0
Package() { 0x001fffff, 0, 0, 17 },
Package() { 0x001fffff, 1, 0, 23 },
Package() { 0x001fffff, 2, 0, 16 },
Package() { 0x001fffff, 3, 0, 18 },
})
} Else {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
})
}
}

1
src/mainboard/google/link/dsdt.asl
View File

@ -44,7 +44,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include "acpi/sandybridge_pci_irqs.asl"
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

64
src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl
View File

@ -1,64 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* This is board specific information: IRQ routing for Sandybridge */
// PCI Interrupt Routing
Method(_PRT)
{
If (PICM) {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, 0, 16 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, 0, 16 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, 0, 19 },
Package() { 0x001cffff, 1, 0, 20 },
Package() { 0x001cffff, 2, 0, 17 },
Package() { 0x001cffff, 3, 0, 18 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, 0, 19 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, 0, 21 },
// LPC devices 0:1f.0
Package() { 0x001fffff, 0, 0, 17 },
Package() { 0x001fffff, 1, 0, 23 },
Package() { 0x001fffff, 2, 0, 16 },
Package() { 0x001fffff, 3, 0, 18 },
})
} Else {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
})
}
}

1
src/mainboard/google/parrot/dsdt.asl
View File

@ -43,7 +43,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include "acpi/sandybridge_pci_irqs.asl"
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

68
src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl
View File

@ -1,68 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* This is board specific information: IRQ routing for Sandybridge */
// PCI Interrupt Routing
Method(_PRT)
{
If (PICM) {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, 0, 16 },
// XHCI 0:14.0
Package() { 0x0014ffff, 0, 0, 19 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, 0, 16 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, 0, 19 },
Package() { 0x001cffff, 1, 0, 20 },
Package() { 0x001cffff, 2, 0, 17 },
Package() { 0x001cffff, 3, 0, 18 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, 0, 19 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, 0, 21 },
// LPC devices 0:1f.0
Package() { 0x001fffff, 0, 0, 17 },
Package() { 0x001fffff, 1, 0, 23 },
Package() { 0x001fffff, 2, 0, 16 },
Package() { 0x001fffff, 3, 0, 18 },
})
} Else {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// XHCI 0:14.0
Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
})
}
}

1
src/mainboard/google/stout/dsdt.asl
View File

@ -44,7 +44,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include "acpi/sandybridge_pci_irqs.asl"
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

1
src/mainboard/hp/2570p/dsdt.asl
View File

@ -39,7 +39,6 @@ DefinitionBlock(
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
}
}
}

1
src/mainboard/hp/2760p/dsdt.asl
View File

@ -39,7 +39,6 @@ DefinitionBlock(
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
}
}
}

1
src/mainboard/hp/8460p/dsdt.asl
View File

@ -39,7 +39,6 @@ DefinitionBlock(
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
}
}
}

1
src/mainboard/hp/8470p/dsdt.asl
View File

@ -39,7 +39,6 @@ DefinitionBlock(
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
}
}
}

1
src/mainboard/intel/emeraldlake2/dsdt.asl
View File

@ -43,7 +43,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

1
src/mainboard/kontron/ktqm77/dsdt.asl
View File

@ -44,7 +44,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

1
src/mainboard/lenovo/l520/dsdt.asl
View File

@ -26,7 +26,6 @@ DefinitionBlock(
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
}
}
}

1
src/mainboard/lenovo/s230u/dsdt.asl
View File

@ -24,7 +24,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}
}

1
src/mainboard/lenovo/t420/dsdt.asl
View File

@ -45,7 +45,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

1
src/mainboard/lenovo/t420s/dsdt.asl
View File

@ -46,7 +46,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

1
src/mainboard/lenovo/t430/dsdt.asl
View File

@ -38,7 +38,6 @@ DefinitionBlock(
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
}
}
}

1
src/mainboard/lenovo/t430s/dsdt.asl
View File

@ -46,7 +46,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

1
src/mainboard/lenovo/t520/dsdt.asl
View File

@ -45,7 +45,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

1
src/mainboard/lenovo/t530/dsdt.asl
View File

@ -45,7 +45,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

1
src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl
View File

@ -45,7 +45,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

1
src/mainboard/lenovo/x201/dsdt.asl
View File

@ -45,7 +45,6 @@ DefinitionBlock(
{
#include <northbridge/intel/nehalem/acpi/nehalem.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

1
src/mainboard/lenovo/x220/dsdt.asl
View File

@ -45,7 +45,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

1
src/mainboard/lenovo/x230/dsdt.asl
View File

@ -45,7 +45,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

1
src/mainboard/packardbell/ms2290/dsdt.asl
View File

@ -39,7 +39,6 @@ DefinitionBlock(
{
#include <northbridge/intel/nehalem/acpi/nehalem.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

1
src/mainboard/roda/rv11/dsdt.asl
View File

@ -42,7 +42,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <acpi/brightness_levels.asl>
}

64
src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl
View File

@ -1,64 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* This is board specific information: IRQ routing for Sandybridge */
// PCI Interrupt Routing
Method(_PRT)
{
If (PICM) {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, 0, 16 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, 0, 22 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, 0, 17 },
Package() { 0x001cffff, 1, 0, 18 },
Package() { 0x001cffff, 2, 0, 19 },
Package() { 0x001cffff, 3, 0, 16 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, 0, 19 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, 0, 17 },
// LPC devices 0:1f.0
Package() { 0x001fffff, 0, 0, 16 },
Package() { 0x001fffff, 1, 0, 22 },
Package() { 0x001fffff, 2, 0, 23 },
Package() { 0x001fffff, 3, 0, 17 },
})
} Else {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKB, 0 },
})
}
}

1
src/mainboard/samsung/lumpy/dsdt.asl
View File

@ -43,7 +43,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include "acpi/sandybridge_pci_irqs.asl"
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

64
src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl
View File

@ -1,64 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* This is board specific information: IRQ routing for Sandybridge */
// PCI Interrupt Routing
Method(_PRT)
{
If (PICM) {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, 0, 16 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, 0, 22 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, 0, 17 },
Package() { 0x001cffff, 1, 0, 18 },
Package() { 0x001cffff, 2, 0, 19 },
Package() { 0x001cffff, 3, 0, 20 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, 0, 19 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, 0, 20 },
// LPC devices 0:1f.0
Package() { 0x001fffff, 0, 0, 21 },
Package() { 0x001fffff, 1, 0, 22 },
Package() { 0x001fffff, 2, 0, 23 },
Package() { 0x001fffff, 3, 0, 16 },
})
} Else {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
})
}
}

1
src/mainboard/samsung/stumpy/dsdt.asl
View File

@ -44,7 +44,6 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include "acpi/sandybridge_pci_irqs.asl"
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

1
src/mainboard/sapphire/pureplatinumh61/dsdt.asl
View File

@ -40,7 +40,6 @@ DefinitionBlock(
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
}
}
}

1
src/southbridge/intel/bd82x6x/Kconfig
View File

@ -25,6 +25,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select SOUTHBRIDGE_INTEL_COMMON
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI
select IOAPIC

77
src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl
View File

@ -1,77 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* PCI Interrupt Routing */
Method(_PRT)
{
If (PICM) {
Return (Package() {
/* Onboard graphics (IGD) 0:2.0 */
Package() { 0x0002ffff, 0, 0, 16 },/* GFX INTA -> PIRQA (MSI) */
/* PCI Express Graphics (PEG) 0:1.0 */
Package() { 0x0001ffff, 0, 0, 16 },/* GFX PCIe INTA -> PIRQA (MSI) */
Package() { 0x0001ffff, 0, 0, 17 },/* GFX PCIe INTB -> PIRQB (MSI) */
Package() { 0x0001ffff, 0, 0, 18 },/* GFX PCIe INTC -> PIRQC (MSI) */
Package() { 0x0001ffff, 0, 0, 19 },/* GFX PCIe INTD -> PIRQD (MSI) */
/* XHCI 0:14.0 (ivy only) */
Package() { 0x0014ffff, 0, 0, 19 },
/* High Definition Audio 0:1b.0 */
Package() { 0x001bffff, 0, 0, 16 },/* D27IP_ZIP HDA INTA -> PIRQA (MSI) */
/* PCIe Root Ports 0:1c.x */
Package() { 0x001cffff, 0, 0, 17 },/* D28IP_P1IP PCIe INTA -> PIRQB */
Package() { 0x001cffff, 1, 0, 21 },/* D28IP_P2IP PCIe INTB -> PIRQF */
Package() { 0x001cffff, 2, 0, 19 },/* D28IP_P3IP PCIe INTC -> PIRQD */
Package() { 0x001cffff, 3, 0, 20 },/* D28IP_P3IP PCIe INTD -> PIRQE */
/* EHCI #1 0:1d.0 */
Package() { 0x001dffff, 0, 0, 19 },/* D29IP_E1P EHCI1 INTA -> PIRQD */
/* EHCI #2 0:1a.0 */
Package() { 0x001affff, 0, 0, 21 },/* D26IP_E2P EHCI2 INTA -> PIRQF */
/* LPC devices 0:1f.0 */
Package() { 0x001fffff, 0, 0, 17 }, /* D31IP_SIP SATA INTA -> PIRQB (MSI) */
Package() { 0x001fffff, 1, 0, 23 }, /* D31IP_SMIP SMBUS INTB -> PIRQH */
Package() { 0x001fffff, 2, 0, 16 }, /* D31IP_TTIP THRT INTC -> PIRQA */
Package() { 0x001fffff, 3, 0, 18 },
})
} Else {
Return (Package() {
/* Onboard graphics (IGD) 0:2.0 */
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
/* PCI Express Graphics (PEG) 0:1.0 */
Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
/* XHCI 0:14.0 (ivy only) */
Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
/* High Definition Audio 0:1b.0 */
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
/* PCIe Root Ports 0:1c.x */
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
/* EHCI #1 0:1d.0 */
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
/* EHCI #2 0:1a.0 */
Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
/* LPC device 0:1f.0 */
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
})
}
}

2
src/southbridge/intel/bd82x6x/lpc.c
View File

@ -35,6 +35,7 @@
#include "pch.h"
#include "nvs.h"
#include <southbridge/intel/common/pciehp.h>
#include <southbridge/intel/common/acpi_pirq_gen.h>
#define NMI_OFF 0
@ -821,6 +822,7 @@ static void southbridge_fill_ssdt(device_t device)
config_t *chip = dev->chip_info;
intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
intel_acpi_gen_def_acpi_pirq(dev);
}
static void lpc_final(struct device *dev)