From 7f61fb99d5b8db186a2893c2bd6807f6316f8a81 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Thu, 28 Dec 2017 20:22:50 -0800 Subject: [PATCH] mainboard/google/zoombini: Fix some devicetree pci settings - Enable I2C #2, #3, and #5 - Enable UART #2 - Enable GSPI #0 and #1 - Disable SATA - Set pci 1f.0 to chromeec BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: Ie29652beff36f19a59746a1ad5f8e7f995ef1281 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/23034 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../zoombini/variants/baseboard/devicetree.cb | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb index e71f15b8cf..771bab2af1 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb @@ -16,18 +16,18 @@ chip soc/intel/cannonlake device pci 14.5 on end # SDCard device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA + device pci 17.0 off end # SATA device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 + device pci 19.1 on end # I2C #5 + device pci 19.2 off end # UART #2 device pci 1a.0 on end # eMMC device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN @@ -44,11 +44,11 @@ chip soc/intel/cannonlake device pci 1d.7 off end # PCI Express Port 16 device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 + device pci 1e.2 on end # GSPI #0 + device pci 1e.3 on end # GSPI #1 device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end + chip ec/google/chromeec + device pnp 0c09.0 on end end end # LPC Interface device pci 1f.1 on end # P2SB