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sb/intel/lynxpoint: Enable/disable AER via Kconfig 

Several changes[1][2] to the Linux kernel now enable ASPM/AER for the
rt8169 network driver, for which it was previously disabled. This,
coupled with the southbridge enabling AER for all PCIe devices, has
resulted in a large amount of AER timeout errors in the kernel log for
boards which utilize the rt8169 for on-board Ethernet (e.g., google/beltino).
While performance is not impacted, the errors do accumulate.

To mitigate this, guard AER enablement via Kconfig, select it by default
(as to maintain current default behavior), and allow boards which need
to disable it to do so (implemented in subsequent commits).

This implementation is derived from that in soc/intel/broadwell.

Test: build/boot google/beltino variants with AER disabled (CB:46136),
verify dmesg log free of AER timeout errors.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=671646c151d492c3846e6e6797e72ff757b5d65e
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=a99790bf5c7f3d68d8b01e015d3212a98ee7bd57

Change-Id: Ia03ef0d111335892c65122954c1248191ded7cb8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46133
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier 2020-10-07 13:11:58 -05:00 committed by Patrick Georgi
parent d0aa999b57
commit 7f6335324b
2 changed files with 9 additions and 2 deletions
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4
src/southbridge/intel/lynxpoint/Kconfig
View File

@ -58,4 +58,8 @@ config FINALIZE_USB_ROUTE_XHCI
If you set this option to y, the USB ports will be routed
to the XHCI controller during the finalize SMM callback.
config PCIEXP_AER
bool
default y
endif

7
src/southbridge/intel/lynxpoint/pcie.c
View File

@ -670,8 +670,11 @@ static void pch_pcie_early(struct device *dev)
/* Set EOI forwarding disable. */
pci_or_config32(dev, 0xd4, 1 << 1);
/* Set something involving advanced error reporting. */
pci_update_config32(dev, 0x100, ~((1 << 20) - 1), 0x10001);
/* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
if (CONFIG(PCIEXP_AER))
pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29) | 0x10001);
else
pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29));
if (is_lp)
pci_or_config32(dev, 0x100, 1 << 29);