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soc/intel/apollolake: Update stage link addresses for 768 KiB cache 

Update link addresses for romstage and verstage. Also update FSP-M relocation
address.

BUG=chrome-os-partner:51959

Change-Id: Ia51a341f05b33151ea5fda9f8620408b5a15bc19
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15454
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Andrey Petrov 2016-06-24 18:15:09 -07:00 committed by Martin Roth
parent 0dde2917a5
commit 7f72c9b30e
1 changed files with 3 additions and 3 deletions
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6
src/soc/intel/apollolake/Kconfig
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@ -145,13 +145,13 @@ config X86_TOP4G_BOOTMEDIA_MAP
config ROMSTAGE_ADDR
hex
default 0xfef3e000
default 0xfef20000
help
The base address (in CAR) where romstage should be linked
config VERSTAGE_ADDR
hex
default 0xfef60000
default 0xfef40000
help
The base address (in CAR) where verstage should be linked
@ -161,7 +161,7 @@ config CACHE_MRC_SETTINGS
config FSP_M_ADDR
hex
default 0xfef60000
default 0xfef40000
help
The address FSP-M will be relocated to during build time