cpu/intel/model_{2065x,206ax}: fix AES-NI locking

MSR_FEATURE_CONFIG, which is used for locking AES-NI, is core-scoped,
not package-scoped. Thus, move locking from SMM to core init, where the
code gets executed once per core.

Change-Id: I3a6f7fc95ce226ce4246b65070726087eb9d689c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/cpu/intel/model_2065x/finalize.c

@@ -16,10 +16,6 @@ void intel_model_2065x_finalize_smm(void)
 	/* Lock C-State MSR */
 	msr_set(MSR_PKG_CST_CONFIG_CONTROL, BIT(15));
 
-	/* Lock AES-NI only if supported */
-	if (cpuid_ecx(1) & (1 << 25))
-		msr_set(MSR_FEATURE_CONFIG, BIT(0));
-
 	/* Lock TM interrupts - route thermal events to all processors */
 	msr_set(MSR_MISC_PWR_MGMT, BIT(22));
 }

src/cpu/intel/model_2065x/model_2065x_init.c

@@ -216,6 +216,12 @@ static void model_2065x_init(struct device *cpu)
 	/* Set virtualization based on Kconfig option */
 	set_vmx_and_lock();
 
+	if (!intel_ht_sibling()) {
+		/* Lock AES-NI only if supported */
+		if (cpuid_ecx(1) & (1 << 25))
+			msr_set(MSR_FEATURE_CONFIG, BIT(0));
+	}
+
 	/* Configure Enhanced SpeedStep and Thermal Sensors */
 	configure_misc();
 

src/cpu/intel/model_206ax/finalize.c

@@ -12,10 +12,6 @@
 
 void intel_model_206ax_finalize_smm(void)
 {
-	/* Lock AES-NI only if supported */
-	if (cpuid_ecx(1) & (1 << 25))
-		msr_set(MSR_FEATURE_CONFIG, BIT(0));
-
 	/* Lock TM interrupts - route thermal events to all processors */
 	msr_set(MSR_MISC_PWR_MGMT, BIT(22));
 

src/cpu/intel/model_206ax/model_206ax_init.c

@@ -470,6 +470,12 @@ static void model_206ax_init(struct device *cpu)
 	/* Thermal throttle activation offset */
 	configure_thermal_target();
 
+	if (!intel_ht_sibling()) {
+		/* Lock AES-NI only if supported */
+		if (cpuid_ecx(1) & (1 << 25))
+			msr_set(MSR_FEATURE_CONFIG, BIT(0));
+	}
+
 	/* Enable Direct Cache Access */
 	configure_dca_cap();