rockchip/rk3399: Move big CPU cluster initialization into ramstage

This patch moves the big CPU cluster initialization on the RK3399 from
the clock init bootblock function into ramstage. We're only really doing
this to put the cluster into a sane state for the OS, we're never
actually taking it out of reset ourselves... so there's no reason to do
this so early.

Also cleaned up the interface for rkclk_configure_cpu() a bit to make it
more readable.

BRANCH=None
BUG=chrome-os-partner:54906
TEST=Booted Kevin.

Change-Id: I568b891da0abb404760d120cef847737c1f9e3ec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bd7aa7ec3e6d211b17ed61419f80a818cee78919
Original-Change-Id: Ic3d01a51531683b53e17addf1942441663a8ea40
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/377541
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/16698
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Julius Werner 2016-08-29 15:07:58 -07:00 committed by Patrick Georgi
parent a39a5b60b4
commit 7f965891b6
4 changed files with 33 additions and 18 deletions

View File

@ -117,7 +117,7 @@ static void speed_up_boot_cpu(void)
udelay(200);
rkclk_configure_cpu(APLL_1512_MHZ, false);
rkclk_configure_cpu(APLL_1512_MHZ, CPU_CLUSTER_LITTLE);
}
void bootblock_mainboard_init(void)

View File

@ -494,26 +494,32 @@ void rkclk_init(void)
HCLK_PERILP1_PLL_SEL_SHIFT));
}
void rkclk_configure_cpu(enum apll_frequencies apll_freq, bool is_big)
void rkclk_configure_cpu(enum apll_frequencies freq, enum cpu_cluster cluster)
{
u32 aclkm_div;
u32 pclk_dbg_div;
u32 atclk_div;
u32 apll_l_hz;
int con_base = is_big ? 2 : 0;
int parent = is_big ? CLK_CORE_PLL_SEL_ABPLL : CLK_CORE_PLL_SEL_ALPLL;
u32 *pll_con = is_big ? &cru_ptr->apll_b_con[0] :
&cru_ptr->apll_l_con[0];
u32 aclkm_div, atclk_div, pclk_dbg_div, apll_hz;
int con_base, parent;
u32 *pll_con;
apll_l_hz = apll_cfgs[apll_freq]->freq;
switch (cluster) {
case CPU_CLUSTER_LITTLE:
con_base = 0;
parent = CLK_CORE_PLL_SEL_ALPLL;
pll_con = &cru_ptr->apll_l_con[0];
break;
case CPU_CLUSTER_BIG:
default:
con_base = 2;
parent = CLK_CORE_PLL_SEL_ABPLL;
pll_con = &cru_ptr->apll_b_con[0];
break;
}
rkclk_set_pll(pll_con, apll_cfgs[apll_freq]);
apll_hz = apll_cfgs[freq]->freq;
rkclk_set_pll(pll_con, apll_cfgs[freq]);
aclkm_div = div_round_up(apll_l_hz, ACLKM_CORE_HZ) - 1;
pclk_dbg_div = div_round_up(apll_l_hz, PCLK_DBG_HZ) - 1;
atclk_div = div_round_up(apll_l_hz, ATCLK_CORE_HZ) - 1;
aclkm_div = div_round_up(apll_hz, ACLKM_CORE_HZ) - 1;
pclk_dbg_div = div_round_up(apll_hz, PCLK_DBG_HZ) - 1;
atclk_div = div_round_up(apll_hz, ATCLK_CORE_HZ) - 1;
write32(&cru_ptr->clksel_con[con_base],
RK_CLRSETBITS(ACLKM_CORE_DIV_CON_MASK <<

View File

@ -101,9 +101,14 @@ enum apll_frequencies {
APLL_600_MHZ,
};
enum cpu_cluster {
CPU_CLUSTER_LITTLE,
CPU_CLUSTER_BIG,
};
void rkclk_init(void);
int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz);
void rkclk_configure_cpu(enum apll_frequencies apll_freq, bool is_big);
void rkclk_configure_cpu(enum apll_frequencies freq, enum cpu_cluster cluster);
void rkclk_configure_ddr(unsigned int hz);
void rkclk_configure_emmc(void);
void rkclk_configure_i2s(unsigned int hz);

View File

@ -18,6 +18,7 @@
#include <cpu/cpu.h>
#include <device/device.h>
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/display.h>
#include <stddef.h>
#include <stdlib.h>
@ -42,6 +43,9 @@ static void soc_init(device_t dev)
_framebuffer_size);
else
printk(BIOS_INFO, "Display initialization disabled.\n");
/* We don't need big CPUs, but bring them up as a courtesy to Linux. */
rkclk_configure_cpu(APLL_600_MHZ, CPU_CLUSTER_BIG);
}
static struct device_operations soc_ops = {