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soc/intel/broadwell: Move `fill_postcar_frame` to memmap.c 

Other Intel northbridges have this function in this file.

Change-Id: I9f084e760ec438d662484455212b5c40a8448928
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2020-10-13 21:14:32 +02:00
parent cc2708797e
commit 7fa445e385
2 changed files with 14 additions and 13 deletions
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14
src/soc/intel/broadwell/memmap.c
View File

@ -3,6 +3,7 @@
/* Use simple device model for this file even in ramstage */
#define __SIMPLE_DEVICE__
#include <arch/romstage.h>
#include <cbmem.h>
#include <cpu/x86/smm.h>
#include <device/pci.h>
@ -43,3 +44,16 @@ void smm_region(uintptr_t *start, size_t *size)
*start = tseg;
*size = bgsm - tseg;
}
void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.
*/
top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
MTRR_TYPE_WRBACK);
}

13
src/soc/intel/broadwell/romstage/romstage.c
View File

@ -16,19 +16,6 @@
#include <soc/romstage.h>
#include <soc/spi.h>
void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.
*/
top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
MTRR_TYPE_WRBACK);
}
/* Entry from cpu/intel/car/romstage.c. */
void mainboard_romstage_entry(void)
{