diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig
index a571bb50dc..349e9de0f0 100644
--- a/src/mainboard/intel/mtlrvp/Kconfig
+++ b/src/mainboard/intel/mtlrvp/Kconfig
@@ -22,6 +22,10 @@ config CHROMEOS
 	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
 	select HAS_RECOVERY_MRC_CACHE
 
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select INTEL_LPSS_UART_FOR_CONSOLE
+
 config MAINBOARD_DIR
 	default "intel/mtlrvp"
 
@@ -81,4 +85,8 @@ endchoice
 config VBOOT
 	select VBOOT_LID_SWITCH
 
+config UART_FOR_CONSOLE
+	int
+	default 0
+
 endif # BOARD_INTEL_MTLRVP_COMMON
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
index 10b4cea335..d28b7b1970 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
@@ -11,6 +11,12 @@ chip soc/intel/meteorlake
 	# EC memory map range is 0x900-0x9ff
 	register "gen3_dec" = "0x00fc0901"
 
+	register "serial_io_uart_mode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
 	device domain 0 on
 		device ref igpu on end
 		device ref heci1 on end