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mb/google/sarien: Reserve gpio pins for D3 cold control 

Based on HW change, reserve gpio pins for D3 cold control.
A13,A15 for Card reader
H13 for M.2 SSD

BUG=b:123263562
TEST=N/A

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib4245be8d77c015e56df7b1d53ef82722c51d656
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Eric Lai 2019-04-08 17:14:36 +08:00 committed by Patrick Georgi
parent 67d630945b
commit 7fc25c013b
1 changed files with 4 additions and 4 deletions
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8
src/mainboard/google/sarien/variants/sarien/gpio.c
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@ -31,9 +31,9 @@ static const struct pad_config gpio_table[] = {
/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE),
/* PME# */ PAD_NC(GPP_A11, NONE),
/* BM_BUSY# */ PAD_NC(GPP_A12, NONE),
/* SUSWARN# */ PAD_NC(GPP_A13, NONE),
/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 0, DEEP), /* Card reader D3 cold */
/* ESPI_RESET# */
/* SUSACK# */ PAD_NC(GPP_A15, NONE),
/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), /* Card reader D3 cold */
/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE),
/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE),
/* ISH_GP0 */ PAD_NC(GPP_A18, NONE),
@ -197,8 +197,8 @@ static const struct pad_config gpio_table[] = {
/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
/* I2C5_SDA */ PAD_NC(GPP_H10, NONE),
/* I2C5_SCL */ PAD_NC(GPP_H11, NONE),
/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE),
/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE),
/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* /D3 cold RST */
/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */
/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE),
/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */
/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE),