From 7fcaf77c2ddb622a1a15c6d49d2f7a550ae6bd6e Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Sun, 14 Feb 2016 15:18:14 -0800 Subject: [PATCH] mainboard/intel/galileo: Disable the remaining PCI devices Add additional lines to the devicetree.cb file to disable the PCI devices in the Quark SoC. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * Devices show up as disabled in BS_DEV_ENUMERATE state or ramstage Change-Id: I1edbbcb88cef29ce972ef054c82e37bf07c3761d Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/13720 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/intel/galileo/devicetree.cb | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb index ab4f246fda..debecc10e1 100644 --- a/src/mainboard/intel/galileo/devicetree.cb +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -18,7 +18,20 @@ chip soc/intel/quark device domain 0 on # EDS Table 3 - device pci 00.0 on end # 8086 0958 - Host Bridge - device pci 1f.0 on end # 8086 095e - Legacy Bridge + device pci 00.0 on end # 8086 0958 - Host Bridge + device pci 14.0 off end # 8086 08A7 - SD/SDIO/eMMC controller + device pci 14.1 off end # 8086 0936 - HSUART 0 + device pci 14.2 off end # 8086 0939 - USB 2.0 Device port + device pci 14.3 off end # 8086 0939 - USB EHCI Host controller + device pci 14.4 off end # 8086 093A - USB OHCI Host controller + device pci 14.5 off end # 8086 0936 - HSUART 1 + device pci 14.6 off end # 8086 0937 - 10/100 Ethernet MAC 0 + device pci 14.7 off end # 8086 0937 - 10/100 Ethernet MAC 1 + device pci 15.0 off end # 8086 0935 - SPI controller 0 + device pci 15.1 off end # 8086 0935 - SPI controller 1 + device pci 15.2 off end # 8086 0934 - I2C/GPIO controller + device pci 17.0 off end # 8086 11C3 - PCIe Root Port 0 + device pci 17.1 off end # 8086 11C4 - PCIe Root Port 1 + device pci 1f.0 on end # 8086 095E - Legacy Bridge end end