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device/device.h: Rename busses for clarity

Browse source 
This renames bus to upstream and link_list to downstream.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans 2023-08-24 15:12:19 +02:00 committed by Felix Held
parent 3138faa7cf
commit 7fcd4d58ec
104 changed files with 343 additions and 348 deletions
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4
src/acpi/acpi.c
View file

@ -700,8 +700,8 @@ void acpi_create_ipmi(const struct device *device,
if (device->path.type == DEVICE_PATH_PCI) {
spmi->pci_device_flag = ACPI_IPMI_PCI_DEVICE_FLAG;
spmi->pci_segment_group = device->bus->segment_group;
spmi->pci_bus = device->bus->secondary;
spmi->pci_segment_group = device->upstream->segment_group;
spmi->pci_bus = device->upstream->secondary;
spmi->pci_device = device->path.pci.devfn >> 3;
spmi->pci_function = device->path.pci.devfn & 0x7;
} else if (type != IPMI_INTERFACE_SSIF) {

12
src/acpi/device.c
View file

@ -83,8 +83,8 @@ const char *acpi_device_name(const struct device *dev)
}
/* Walk up the tree to find if any parent can identify this device */
while (pdev->bus) {
pdev = pdev->bus->dev;
while (pdev->upstream) {
pdev = pdev->upstream->dev;
if (!pdev)
break;
if (is_root_device(pdev))
@ -147,8 +147,8 @@ static ssize_t acpi_device_path_fill(const struct device *dev, char *buf,
return cur;
/* Walk up the tree to the root device */
if (!is_root_device(dev) && dev->bus && dev->bus->dev)
next = acpi_device_path_fill(dev->bus->dev, buf, buf_len, cur);
if (!is_root_device(dev) && dev->upstream && dev->upstream->dev)
next = acpi_device_path_fill(dev->upstream->dev, buf, buf_len, cur);
if (next < 0)
return next;
@ -182,10 +182,10 @@ const char *acpi_device_scope(const struct device *dev)
{
static char buf[DEVICE_PATH_MAX] = {};
if (!dev || !dev->bus || !dev->bus->dev)
if (!dev || !dev->upstream || !dev->upstream->dev)
return NULL;
if (acpi_device_path_fill(dev->bus->dev, buf, sizeof(buf), 0) <= 0)
if (acpi_device_path_fill(dev->upstream->dev, buf, sizeof(buf), 0) <= 0)
return NULL;
return buf;

8
src/arch/x86/mpspec.c
View file

@ -284,11 +284,11 @@ void smp_write_intsrc_pci_bridge(struct mp_config_table *mc,
unsigned char dstirq_x[4];
if (!dev->link_list)
if (!dev->downstream)
return;
child = dev->link_list->children;
srcbus = dev->link_list->secondary;
child = dev->downstream->children;
srcbus = dev->downstream->secondary;
while (child) {
if (child->path.type != DEVICE_PATH_PCI)
@ -476,7 +476,7 @@ void mptable_write_buses(struct mp_config_table *mc, int *max_pci_bus,
memset(buses, 0, sizeof(buses));
for (dev = all_devices; dev; dev = dev->next) {
struct bus *bus = dev->link_list;
struct bus *bus = dev->downstream;
if (!bus)
continue;
if (bus->secondary > 255) {

2
src/cpu/intel/haswell/haswell_init.c
View file

@ -449,7 +449,7 @@ static void configure_c_states(void)
static void configure_thermal_target(struct device *dev)
{
/* Make sure your devicetree has the cpu_cluster below chip cpu/intel/haswell! */
struct cpu_intel_haswell_config *conf = dev->bus->dev->chip_info;
struct cpu_intel_haswell_config *conf = dev->upstream->dev->chip_info;
msr_t msr;
/* Set TCC activation offset if supported */

2
src/cpu/intel/model_2065x/model_2065x_init.c
View file

@ -22,7 +22,7 @@
static void configure_thermal_target(struct device *dev)
{
struct cpu_intel_model_2065x_config *conf = dev->bus->dev->chip_info;
struct cpu_intel_model_2065x_config *conf = dev->upstream->dev->chip_info;
msr_t msr;
/* Set TCC activation offset if supported */

2
src/cpu/intel/model_206ax/model_206ax_init.c
View file

@ -223,7 +223,7 @@ static void configure_c_states(void)
static void configure_thermal_target(struct device *dev)
{
struct cpu_intel_model_206ax_config *conf = dev->bus->dev->chip_info;
struct cpu_intel_model_206ax_config *conf = dev->upstream->dev->chip_info;
msr_t msr;
if (boot_cpu()) {

2
src/device/cardbus_device.c
View file

@ -119,7 +119,7 @@ void cardbus_enable_resources(struct device *dev)
u16 ctrl;
ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
ctrl |= (dev->link_list->bridge_ctrl & (
ctrl |= (dev->downstream->bridge_ctrl & (
PCI_BRIDGE_CTL_VGA |
PCI_BRIDGE_CTL_MASTER_ABORT |
PCI_BRIDGE_CTL_BUS_RESET));

50
src/device/device.c
View file

@ -101,7 +101,7 @@ static struct device *__alloc_dev(struct bus *parent, struct device_path *path)
dev->enabled = 1;
/* Add the new device to the list of children of the bus. */
dev->bus = parent;
dev->upstream = parent;
if (child)
child->sibling = dev;
else
@ -139,13 +139,13 @@ DECLARE_SPIN_LOCK(bus_lock)
*/
static struct bus *__alloc_bus(struct device *parent)
{
if (parent->link_list)
return parent->link_list;
if (parent->downstream)
return parent->downstream;
struct bus *bus = calloc(1, sizeof(struct bus));
if (!bus)
die("Couldn't allocate downstream bus!\n");
parent->link_list = bus;
parent->downstream = bus;
bus->dev = parent;
return bus;
@ -205,8 +205,8 @@ static void read_resources(struct bus *bus)
curdev->ops->read_resources(curdev);
/* Read in the resources behind the current device's links. */
if (curdev->link_list)
read_resources(curdev->link_list);
if (curdev->downstream)
read_resources(curdev->downstream);
}
post_log_clear();
printk(BIOS_SPEW, "%s %s segment group %d bus %d done\n",
@ -236,7 +236,7 @@ static void set_vga_bridge_bits(void)
continue;
printk(BIOS_DEBUG, "found VGA at %s\n", dev_path(dev));
if (dev->bus->no_vga16) {
if (dev->upstream->no_vga16) {
printk(BIOS_WARNING,
"A bridge on the path doesn't support 16-bit VGA decoding!");
}
@ -270,7 +270,7 @@ static void set_vga_bridge_bits(void)
/* All legacy VGA cards have MEM & I/O space registers. */
vga->command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
vga_pri = vga;
bus = vga->bus;
bus = vga->upstream;
}
/* Now walk up the bridges setting the VGA enable. */
@ -278,7 +278,7 @@ static void set_vga_bridge_bits(void)
printk(BIOS_DEBUG, "Setting PCI_BRIDGE_CTL_VGA for bridge %s\n",
dev_path(bus->dev));
bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_VGA16;
bus = (bus == bus->dev->bus) ? 0 : bus->dev->bus;
bus = (bus == bus->dev->upstream) ? 0 : bus->dev->upstream;
}
}
@ -343,8 +343,8 @@ static void enable_resources(struct bus *link)
}
for (dev = link->children; dev; dev = dev->sibling) {
if (dev->link_list)
enable_resources(dev->link_list);
if (dev->downstream)
enable_resources(dev->downstream);
}
post_log_clear();
}
@ -391,7 +391,7 @@ static void scan_bus(struct device *busdev)
do_scan_bus = 1;
while (do_scan_bus) {
struct bus *link = busdev->link_list;
struct bus *link = busdev->downstream;
busdev->ops->scan_bus(busdev);
do_scan_bus = 0;
if (!link || !link->reset_needed)
@ -399,7 +399,7 @@ static void scan_bus(struct device *busdev)
if (reset_bus(link))
do_scan_bus = 1;
else
busdev->bus->reset_needed = 1;
busdev->upstream->reset_needed = 1;
}
scan_time = stopwatch_duration_msecs(&sw);
@ -496,14 +496,14 @@ void dev_configure(void)
/* Read the resources for the entire tree. */
printk(BIOS_INFO, "Reading resources...\n");
read_resources(root->link_list);
read_resources(root->downstream);
printk(BIOS_INFO, "Done reading resources.\n");
print_resource_tree(root, BIOS_SPEW, "After reading.");
allocate_resources(root);
assign_resources(root->link_list);
assign_resources(root->downstream);
printk(BIOS_INFO, "Done setting resources.\n");
print_resource_tree(root, BIOS_SPEW, "After assigning values.");
@ -521,8 +521,8 @@ void dev_enable(void)
printk(BIOS_INFO, "Enabling resources...\n");
/* Now enable everything. */
if (dev_root.link_list)
enable_resources(dev_root.link_list);
if (dev_root.downstream)
enable_resources(dev_root.downstream);
printk(BIOS_INFO, "done.\n");
}
@ -546,7 +546,7 @@ static void init_dev(struct device *dev)
long init_time;
if (dev->path.type == DEVICE_PATH_I2C) {
printk(BIOS_DEBUG, "smbus: %s->", dev_path(dev->bus->dev));
printk(BIOS_DEBUG, "smbus: %s->", dev_path(dev->upstream->dev));
}
printk(BIOS_DEBUG, "%s init\n", dev_path(dev));
@ -572,8 +572,8 @@ static void init_link(struct bus *link)
}
for (dev = link->children; dev; dev = dev->sibling)
if (dev->link_list)
init_link(dev->link_list);
if (dev->downstream)
init_link(dev->downstream);
}
/**
@ -590,8 +590,8 @@ void dev_initialize(void)
init_dev(&dev_root);
/* Now initialize everything. */
if (dev_root.link_list)
init_link(dev_root.link_list);
if (dev_root.downstream)
init_link(dev_root.downstream);
post_log_clear();
printk(BIOS_INFO, "Devices initialized\n");
@ -626,8 +626,8 @@ static void final_link(struct bus *link)
final_dev(dev);
for (dev = link->children; dev; dev = dev->sibling)
if (dev->link_list)
final_link(dev->link_list);
if (dev->downstream)
final_link(dev->downstream);
}
/**
* Finalize all devices in the global device tree.
@ -643,7 +643,7 @@ void dev_finalize(void)
final_dev(&dev_root);
/* Now finalize everything. */
final_link(dev_root.link_list);
final_link(dev_root.downstream);
printk(BIOS_INFO, "Devices finalized\n");
}

16
src/device/device_const.c
View file

@ -34,8 +34,8 @@ static DEVTREE_CONST struct device *dev_find_slot(unsigned int bus,
result = 0;
for (dev = all_devices; dev; dev = dev->next) {
if ((dev->path.type == DEVICE_PATH_PCI) &&
(dev->bus->secondary == bus) &&
(dev->bus->segment_group == 0) &&
(dev->upstream->secondary == bus) &&
(dev->upstream->segment_group == 0) &&
(dev->path.pci.devfn == devfn)) {
result = dev;
break;
@ -210,7 +210,7 @@ DEVTREE_CONST struct device *find_dev_nested_path(
if (nested_path_length == 1 || !child)
return child;
return find_dev_nested_path(child->link_list, nested_path + 1, nested_path_length - 1);
return find_dev_nested_path(child->downstream, nested_path + 1, nested_path_length - 1);
}
DEVTREE_CONST struct device *pcidev_path_behind(
@ -234,8 +234,8 @@ DEVTREE_CONST struct device *pcidev_path_on_bus(unsigned int bus, pci_devfn_t de
dev = dev->next;
continue;
}
if (dev->bus->secondary == bus && dev->bus->segment_group == 0)
return pcidev_path_behind(dev->bus, devfn);
if (dev->upstream->secondary == bus && dev->upstream->segment_group == 0)
return pcidev_path_behind(dev->upstream, devfn);
dev = dev->next;
}
return NULL;
@ -253,7 +253,7 @@ DEVTREE_CONST struct bus *pci_root_bus(void)
if (!pci_domain)
return NULL;
pci_root = pci_domain->link_list;
pci_root = pci_domain->downstream;
return pci_root;
}
@ -277,7 +277,7 @@ DEVTREE_CONST struct device *pcidev_path_behind_pci2pci_bridge(
return NULL;
}
return pcidev_path_behind(bridge->link_list, devfn);
return pcidev_path_behind(bridge->downstream, devfn);
}
DEVTREE_CONST struct device *pcidev_path_on_root_debug(pci_devfn_t devfn, const char *func)
@ -317,7 +317,7 @@ DEVTREE_CONST struct device *dev_find_slot_on_smbus(unsigned int bus,
result = 0;
for (dev = all_devices; dev; dev = dev->next) {
if ((dev->path.type == DEVICE_PATH_I2C) &&
(dev->bus->secondary == bus) &&
(dev->upstream->secondary == bus) &&
(dev->path.i2c.device == addr)) {
result = dev;
break;

49
src/device/device_util.c
View file

@ -97,7 +97,7 @@ u32 dev_path_encode(const struct device *dev)
case DEVICE_PATH_ROOT:
break;
case DEVICE_PATH_PCI:
ret |= dev->bus->segment_group << 16 | dev->bus->secondary << 8 | dev->path.pci.devfn;
ret |= dev->upstream->segment_group << 16 | dev->upstream->secondary << 8 | dev->path.pci.devfn;
break;
case DEVICE_PATH_PNP:
ret |= dev->path.pnp.port << 8 | dev->path.pnp.device;
@ -169,8 +169,8 @@ const char *dev_path(const struct device *dev)
case DEVICE_PATH_PCI:
snprintf(buffer, sizeof(buffer),
"PCI: %02x:%02x:%02x.%01x",
dev->bus->segment_group,
dev->bus->secondary,
dev->upstream->segment_group,
dev->upstream->secondary,
PCI_SLOT(dev->path.pci.devfn),
PCI_FUNC(dev->path.pci.devfn));
break;
@ -180,7 +180,7 @@ const char *dev_path(const struct device *dev)
break;
case DEVICE_PATH_I2C:
snprintf(buffer, sizeof(buffer), "I2C: %02x:%02x",
dev->bus->secondary,
dev->upstream->secondary,
dev->path.i2c.device);
break;
case DEVICE_PATH_APIC:
@ -253,8 +253,8 @@ const char *dev_name(const struct device *dev)
struct device *dev_get_pci_domain(struct device *dev)
{
/* Walk up the tree up to the PCI domain */
while (dev && dev->bus && !is_root_device(dev)) {
dev = dev->bus->dev;
while (dev && dev->upstream && !is_root_device(dev)) {
dev = dev->upstream->dev;
if (dev->path.type == DEVICE_PATH_DOMAIN)
return dev;
}
@ -529,10 +529,10 @@ void report_resource_stored(struct device *dev, const struct resource *resource,
end = resource_end(resource);
buf[0] = '\0';
if (dev->link_list && (resource->flags & IORESOURCE_PCI_BRIDGE)) {
if (dev->downstream && (resource->flags & IORESOURCE_PCI_BRIDGE)) {
snprintf(buf, sizeof(buf),
"seg %02x bus %02x ", dev->link_list->segment_group,
dev->link_list->secondary);
"seg %02x bus %02x ", dev->downstream->segment_group,
dev->downstream->secondary);
}
printk(BIOS_DEBUG, "%s %02lx <- [0x%016llx - 0x%016llx] size 0x%08llx "
"gran 0x%02x %s%s%s\n", dev_path(dev), resource->index,
@ -560,8 +560,8 @@ void search_bus_resources(struct bus *bus, unsigned long type_mask,
/* If it is a subtractive resource recurse. */
if (res->flags & IORESOURCE_SUBTRACTIVE) {
if (curdev->link_list)
search_bus_resources(curdev->link_list, type_mask, type,
if (curdev->downstream)
search_bus_resources(curdev->downstream, type_mask, type,
search, gp);
continue;
}
@ -617,8 +617,8 @@ void disable_children(struct bus *bus)
struct device *child;
for (child = bus->children; child; child = child->sibling) {
if (child->link_list)
disable_children(child->link_list);
if (child->downstream)
disable_children(child->downstream);
dev_set_enabled(child, 0);
}
}
@ -634,10 +634,10 @@ bool dev_is_active_bridge(struct device *dev)
if (!dev || !dev->enabled)
return 0;
if (!dev->link_list || !dev->link_list->children)
if (!dev->downstream || !dev->downstream->children)
return 0;
for (child = dev->link_list->children; child; child = child->sibling) {
for (child = dev->downstream->children; child; child = child->sibling) {
if (child->path.type == DEVICE_PATH_NONE)
continue;
if (child->enabled)
@ -659,9 +659,9 @@ static void resource_tree(const struct device *root, int debug_level, int depth)
indent[i] = '\0';
printk(BIOS_DEBUG, "%s%s", indent, dev_path(root));
if (root->link_list && root->link_list->children)
if (root->downstream && root->downstream->children)
printk(BIOS_DEBUG, " child on link 0 %s",
dev_path(root->link_list->children));
dev_path(root->downstream->children));
printk(BIOS_DEBUG, "\n");
for (res = root->resource_list; res; res = res->next) {
@ -672,10 +672,10 @@ static void resource_tree(const struct device *root, int debug_level, int depth)
res->index);
}
if (!root->link_list)
if (!root->downstream)
return;
for (child = root->link_list->children; child; child = child->sibling)
for (child = root->downstream->children; child; child = child->sibling)
resource_tree(child, debug_level, depth + 1);
}
@ -709,10 +709,10 @@ void show_devs_tree(const struct device *dev, int debug_level, int depth)
printk(debug_level, "%s%s: enabled %d\n",
depth_str, dev_path(dev), dev->enabled);
if (!dev->link_list)
if (!dev->downstream)
return;
for (sibling = dev->link_list->children; sibling; sibling = sibling->sibling)
for (sibling = dev->downstream->children; sibling; sibling = sibling->sibling)
show_devs_tree(sibling, debug_level, depth + 1);
}
@ -890,7 +890,7 @@ const char *dev_path_name(enum device_path_type type)
bool dev_path_hotplug(const struct device *dev)
{
for (dev = dev->bus->dev; dev != dev->bus->dev; dev = dev->bus->dev) {
for (dev = dev->upstream->dev; dev != dev->upstream->dev; dev = dev->upstream->dev) {
if (dev->hotplug_port)
return true;
}
@ -909,7 +909,7 @@ void log_resource(const char *type, const struct device *dev, const struct resou
bool is_cpu(const struct device *cpu)
{
return cpu->path.type == DEVICE_PATH_APIC &&
cpu->bus->dev->path.type == DEVICE_PATH_CPU_CLUSTER;
cpu->upstream->dev->path.type == DEVICE_PATH_CPU_CLUSTER;
}
bool is_enabled_cpu(const struct device *cpu)
@ -929,5 +929,6 @@ bool is_enabled_pci(const struct device *pci)
bool is_pci_dev_on_bus(const struct device *pci, unsigned int bus)
{
return is_pci(pci) && pci->bus->segment_group == 0 && pci->bus->secondary == bus;
return is_pci(pci) && pci->upstream->segment_group == 0
&& pci->upstream->secondary == bus;
}

8
src/device/i2c_bus.c
View file

@ -18,10 +18,10 @@ bool i2c_dev_detect(struct device *dev, unsigned int addr)
struct bus *i2c_link(const struct device *const dev)
{
if (!dev || !dev->bus)
if (!dev || !dev->upstream)
return NULL;
struct bus *link = dev->bus;
struct bus *link = dev->upstream;
while (link) {
struct device *const parent = link->dev;
@ -29,8 +29,8 @@ struct bus *i2c_link(const struct device *const dev)
(parent->ops->ops_i2c_bus || parent->ops->ops_smbus_bus))
break;
if (parent && parent->bus && link != parent->bus)
link = parent->bus;
if (parent && parent->upstream && link != parent->upstream)
link = parent->upstream;
else
link = NULL;
}

4
src/device/mdio.c
View file

@ -19,7 +19,7 @@ const struct mdio_bus_operations *dev_get_mdio_ops(struct device *dev)
uint16_t mdio_read(struct device *dev, uint8_t offset)
{
const struct mdio_bus_operations *mdio_ops;
struct device *parent = dev->bus->dev;
struct device *parent = dev->upstream->dev;
assert(dev->path.type == DEVICE_PATH_MDIO);
mdio_ops = dev_get_mdio_ops(parent);
@ -30,7 +30,7 @@ uint16_t mdio_read(struct device *dev, uint8_t offset)
void mdio_write(struct device *dev, uint8_t offset, uint16_t val)
{
const struct mdio_bus_operations *mdio_ops;
struct device *parent = dev->bus->dev;
struct device *parent = dev->upstream->dev;
assert(dev->path.type == DEVICE_PATH_MDIO);
mdio_ops = dev_get_mdio_ops(parent);

2
src/device/oprom/realmode/x86.c
View file

@ -415,7 +415,7 @@ void vbe_textmode_console(void)
void run_bios(struct device *dev, unsigned long addr)
{
u32 num_dev = (dev->bus->secondary << 8) | dev->path.pci.devfn;
u32 num_dev = (dev->upstream->secondary << 8) | dev->path.pci.devfn;
/* Setting up required hardware.
* Removing this will cause random illegal instruction exceptions

2
src/device/oprom/realmode/x86_interrupts.c
View file

@ -138,7 +138,7 @@ int int1a_handler(void)
X86_EAX |= PCIBIOS_SUCCESSFUL;
// busnum is an unsigned char;
// devfn is an int, so we mask it off.
busdevfn = (dev->bus->secondary << 8)
busdevfn = (dev->upstream->secondary << 8)
| (dev->path.pci.devfn & 0xff);
printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func, busdevfn);
X86_EBX = busdevfn;

2
src/device/oprom/yabel/device.c
View file

@ -65,7 +65,7 @@ biosemu_dev_get_addr_info(void)
{
int taa_index = 0;
struct resource *r;
u8 bus = bios_device.dev->bus->secondary;
u8 bus = bios_device.dev->upstream->secondary;
u16 devfn = bios_device.dev->path.pci.devfn;
bios_device.bus = bus;

2
src/device/oprom/yabel/interrupt.c
View file

@ -375,7 +375,7 @@ handleInt1a(void)
} else if (CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES)) {
dev = dev_find_device(M.x86.R_DX, M.x86.R_CX, 0);
if (dev != NULL) {
M.x86.R_BH = dev->bus->secondary;
M.x86.R_BH = dev->upstream->secondary;
M.x86.R_BL = dev->path.pci.devfn;
DEBUG_PRINTF_INTR
("%s(): function %x: PCI Find Device --> 0x%04x\n",

46
src/device/pci_device.c
View file

@ -585,7 +585,7 @@ void pci_domain_read_resources(struct device *dev)
void pci_domain_set_resources(struct device *dev)
{
assign_resources(dev->link_list);
assign_resources(dev->downstream);
}
static void pci_store_resource(const struct device *const dev,
@ -718,8 +718,8 @@ void pci_dev_set_resources(struct device *dev)
for (res = dev->resource_list; res; res = res->next)
pci_set_resource(dev, res);
if (dev->link_list && dev->link_list->children)
assign_resources(dev->link_list);
if (dev->downstream && dev->downstream->children)
assign_resources(dev->downstream);
/* Set a default latency timer. */
pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
@ -782,10 +782,10 @@ void pci_bus_enable_resources(struct device *dev)
* Enable I/O in command register if there is VGA card
* connected with (even it does not claim I/O resource).
*/
if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
if (dev->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
dev->command |= PCI_COMMAND_IO;
ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
ctrl |= dev->link_list->bridge_ctrl;
ctrl |= dev->downstream->bridge_ctrl;
ctrl |= (PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR); /* Error check. */
printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
@ -843,7 +843,7 @@ static int should_run_oprom(struct device *dev, struct rom_header *rom)
{
static int should_run = -1;
if (dev->bus->segment_group) {
if (dev->upstream->segment_group) {
printk(BIOS_ERR, "Only option ROMs of devices in first PCI segment group can "
"be run.\n");
return 0;
@ -990,7 +990,7 @@ static void pci_bridge_vga_compat(struct bus *const bus)
pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl);
/* If the upstream bridge doesn't support VGA16, we don't have to check */
bus->no_vga16 |= bus->dev->bus->no_vga16;
bus->no_vga16 |= bus->dev->upstream->no_vga16;
if (bus->no_vga16)
return;
@ -1215,7 +1215,7 @@ struct device *pci_probe_dev(struct device *dev, struct bus *bus,
if (!dev) {
struct device dummy;
dummy.bus = bus;
dummy.upstream = bus;
dummy.path.type = DEVICE_PATH_PCI;
dummy.path.pci.devfn = devfn;
@ -1317,9 +1317,9 @@ struct device *pci_probe_dev(struct device *dev, struct bus *bus,
*/
unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev)
{
return dev->bus->secondary == PCI_DEV2BUS(sdev) &&
dev->bus->segment_group == PCI_DEV2SEG(sdev) &&
dev->path.pci.devfn == PCI_DEV2DEVFN(sdev);
return dev->upstream->secondary == PCI_DEV2BUS(sdev) &&
dev->upstream->segment_group == PCI_DEV2SEG(sdev) &&
dev->path.pci.devfn == PCI_DEV2DEVFN(sdev);
}
/**
@ -1333,14 +1333,14 @@ unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev)
*/
uint16_t pci_find_cap_recursive(const struct device *dev, uint16_t cap)
{
assert(dev->bus);
assert(dev->upstream);
uint16_t pos = pci_find_capability(dev, cap);
const struct device *bridge = dev->bus->dev;
const struct device *bridge = dev->upstream->dev;
while (bridge && (bridge->path.type == DEVICE_PATH_PCI)) {
assert(bridge->bus);
assert(bridge->upstream);
if (!pci_find_capability(bridge, cap))
return 0;
bridge = bridge->bus->dev;
bridge = bridge->upstream->dev;
}
return pos;
}
@ -1546,7 +1546,7 @@ typedef enum {
static void pci_bridge_route(struct bus *link, scan_state state)
{
struct device *dev = link->dev;
struct bus *parent = dev->bus;
struct bus *parent = dev->upstream;
uint8_t primary, secondary, subordinate;
if (state == PCI_ROUTE_SCAN) {
@ -1625,17 +1625,17 @@ void do_pci_scan_bridge(struct device *dev,
printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(dev));
if (dev->link_list == NULL) {
if (dev->downstream == NULL) {
struct bus *link;
link = malloc(sizeof(*link));
if (link == NULL)
die("Couldn't allocate a link!\n");
memset(link, 0, sizeof(*link));
link->dev = dev;
dev->link_list = link;
dev->downstream = link;
}
bus = dev->link_list;
bus = dev->downstream;
pci_bridge_vga_compat(bus);
@ -1670,7 +1670,7 @@ void pci_scan_bridge(struct device *dev)
*/
void pci_host_bridge_scan_bus(struct device *dev)
{
struct bus *link = dev->link_list;
struct bus *link = dev->downstream;
pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff);
}
@ -1733,8 +1733,8 @@ static int swizzle_irq_pins(struct device *dev, struct device **parent_bridge)
/* While our current device has parent devices */
child = dev;
for (parent = child->bus->dev; parent; parent = parent->bus->dev) {
parent_bus = parent->bus->secondary;
for (parent = child->upstream->dev; parent; parent = parent->upstream->dev) {
parent_bus = parent->upstream->secondary;
parent_devfn = parent->path.pci.devfn;
child_devfn = child->path.pci.devfn;
@ -1798,7 +1798,7 @@ int get_pci_irq_pins(struct device *dev, struct device **parent_bdg)
if (!(dev->enabled && (dev->path.type == DEVICE_PATH_PCI)))
return -1;
bus = dev->bus->secondary;
bus = dev->upstream->secondary;
devfn = dev->path.pci.devfn;
/* Get and validate the interrupt pin used. Only 1-4 are allowed */

4
src/device/pci_rom.c
View file

@ -230,7 +230,7 @@ ati_rom_acpi_fill_vfct(const struct device *device, acpi_vfct_t *vfct_struct,
printk(BIOS_ERR, "%s failed\n", __func__);
return current;
}
if (device->bus->segment_group) {
if (device->upstream->segment_group) {
printk(BIOS_ERR, "VFCT only supports GPU in first PCI segment group.\n");
return current;
}
@ -243,7 +243,7 @@ ati_rom_acpi_fill_vfct(const struct device *device, acpi_vfct_t *vfct_struct,
header->DeviceID = device->device;
header->VendorID = device->vendor;
header->PCIBus = device->bus->secondary;
header->PCIBus = device->upstream->secondary;
header->PCIFunction = PCI_FUNC(device->path.pci.devfn);
header->PCIDevice = PCI_SLOT(device->path.pci.devfn);
header->ImageLength = rom->size * 512;

10
src/device/pciexp_device.c
View file

@ -302,7 +302,7 @@ static void pciexp_enable_ltr(struct device *dev)
struct device *parent = NULL;
unsigned int parent_cap = 0;
if (!dev->ops->ops_pci || !dev->ops->ops_pci->get_ltr_max_latencies) {
parent = dev->bus->dev;
parent = dev->upstream->dev;
if (parent->path.type != DEVICE_PATH_PCI)
return;
parent_cap = pci_find_capability(parent, PCI_CAP_ID_PCIE);
@ -319,9 +319,9 @@ bool pciexp_get_ltr_max_latencies(struct device *dev, u16 *max_snoop, u16 *max_n
do {
if (dev->ops->ops_pci && dev->ops->ops_pci->get_ltr_max_latencies)
break;
if (dev->bus->dev == dev || dev->bus->dev->path.type != DEVICE_PATH_PCI)
if (dev->upstream->dev == dev || dev->upstream->dev->path.type != DEVICE_PATH_PCI)
return false;
dev = dev->bus->dev;
dev = dev->upstream->dev;
} while (true);
dev->ops->ops_pci->get_ltr_max_latencies(max_snoop, max_nosnoop);
@ -627,7 +627,7 @@ static void clear_lane_error_status(struct device *dev)
static void pciexp_tune_dev(struct device *dev)
{
struct device *root = dev->bus->dev;
struct device *root = dev->upstream->dev;
unsigned int root_cap, cap;
cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
@ -752,7 +752,7 @@ void pciexp_hotplug_scan_bridge(struct device *dev)
/* Add dummy slot to preserve resources, must happen after bus scan */
struct device *dummy;
struct device_path dummy_path = { .type = DEVICE_PATH_NONE };
dummy = alloc_dev(dev->link_list, &dummy_path);
dummy = alloc_dev(dev->downstream, &dummy_path);
dummy->ops = &pciexp_hotplug_dummy_ops;
}

6
src/device/pcix_device.c
View file

@ -107,11 +107,11 @@ void pcix_scan_bridge(struct device *dev)
sstatus = pci_read_config16(dev, pos + PCI_X_SEC_STATUS);
if (PCI_X_SSTATUS_MFREQ(sstatus) != PCI_X_SSTATUS_CONVENTIONAL_PCI)
pcix_tune_bus(dev->link_list);
pcix_tune_bus(dev->downstream);
/* Print the PCI-X bus speed. */
printk(BIOS_DEBUG, "PCI: %02x:%02x: %s\n", dev->link_list->segment_group,
dev->link_list->secondary, pcix_speed(sstatus));
printk(BIOS_DEBUG, "PCI: %02x:%02x: %s\n", dev->downstream->segment_group,
dev->downstream->secondary, pcix_speed(sstatus));
}
/** Default device operations for PCI-X bridges */

2
src/device/pnp_device.c
View file

@ -384,7 +384,7 @@ void pnp_enable_devices(struct device *base_dev, struct device_operations *ops,
continue;
path.pnp.device = info[i].function;
dev = alloc_find_dev(base_dev->bus, &path);
dev = alloc_find_dev(base_dev->upstream, &path);
/* Don't initialize a device multiple times. */
if (dev->ops)

22
src/device/resource_allocator_v4.c
View file

@ -78,7 +78,7 @@ static void print_resource_ranges(const struct device *dev, const struct memrang
static bool dev_has_children(const struct device *dev)
{
const struct bus *bus = dev->link_list;
const struct bus *bus = dev->downstream;
return bus && bus->children;
}
@ -122,7 +122,7 @@ static void update_bridge_resource(const struct device *bridge, struct resource
resource_t base;
const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH;
const unsigned long type_match = bridge_res->flags & type_mask;
struct bus *bus = bridge->link_list;
struct bus *bus = bridge->downstream;
child_res = NULL;
@ -208,7 +208,7 @@ static void compute_bridge_resources(const struct device *bridge, unsigned long
{
const struct device *child;
struct resource *res;
struct bus *bus = bridge->link_list;
struct bus *bus = bridge->downstream;
const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH;
for (res = bridge->resource_list; res; res = res->next) {
@ -256,10 +256,10 @@ static void compute_domain_resources(const struct device *domain)
const struct device *child;
const int print_depth = 1;
if (domain->link_list == NULL)
if (domain->downstream == NULL)
return;
for (child = domain->link_list->children; child; child = child->sibling) {
for (child = domain->downstream->children; child; child = child->sibling) {
/* Skip if this is not a bridge or has no children under it. */
if (!dev_has_children(child))
@ -299,7 +299,7 @@ static void avoid_fixed_resources(struct memranges *ranges, const struct device
memranges_create_hole(ranges, res->base, res->size);
}
bus = dev->link_list;
bus = dev->downstream;
if (bus == NULL)
return;
@ -399,7 +399,7 @@ static void allocate_toplevel_resources(const struct device *const domain,
setup_resource_ranges(domain, type, &ranges);
while ((dev = largest_resource(domain->link_list, &res, type_mask, type))) {
while ((dev = largest_resource(domain->downstream, &res, type_mask, type))) {
if (!res->size)
continue;
@ -441,7 +441,7 @@ static void allocate_bridge_resources(const struct device *bridge)
{
const unsigned long type_mask =
IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH | IORESOURCE_FIXED;
struct bus *const bus = bridge->link_list;
struct bus *const bus = bridge->downstream;
struct resource *res;
struct device *child;
@ -496,7 +496,7 @@ static void allocate_domain_resources(const struct device *domain)
allocate_toplevel_resources(domain, IORESOURCE_MEM);
struct device *child;
for (child = domain->link_list->children; child; child = child->sibling) {
for (child = domain->downstream->children; child; child = child->sibling) {
if (!dev_has_children(child))
continue;
@ -553,10 +553,10 @@ void allocate_resources(const struct device *root)
{
const struct device *child;
if ((root == NULL) || (root->link_list == NULL))
if ((root == NULL) || (root->downstream == NULL))
return;
for (child = root->link_list->children; child; child = child->sibling) {
for (child = root->downstream->children; child; child = child->sibling) {
if (child->path.type != DEVICE_PATH_DOMAIN)
continue;

16
src/device/root_device.c
View file

@ -39,10 +39,10 @@ void enable_static_devices(struct device *bus)
{
struct device *child;
if (!bus->link_list)
if (!bus->downstream)
return;
for (child = bus->link_list->children; child; child = child->sibling)
for (child = bus->downstream->children; child; child = child->sibling)
enable_static_device(child);
}
@ -53,12 +53,12 @@ void scan_generic_bus(struct device *bus)
printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus));
if (bus->link_list) {
bus->link_list->secondary = ++bus_max;
if (bus->downstream) {
bus->downstream->secondary = ++bus_max;
for (child = bus->link_list->children; child; child = child->sibling) {
for (child = bus->downstream->children; child; child = child->sibling) {
enable_static_device(child);
printk(BIOS_DEBUG, "bus: %s->", dev_path(child->bus->dev));
printk(BIOS_DEBUG, "bus: %s->", dev_path(child->upstream->dev));
}
}
@ -86,8 +86,8 @@ void scan_static_bus(struct device *bus)
enable_static_devices(bus);
if (bus->link_list)
scan_bridges(bus->link_list);
if (bus->downstream)
scan_bridges(bus->downstream);
printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus));
}

4
src/drivers/i2c/ptn3460/ptn3460.c
View file

@ -172,8 +172,8 @@ static void ptn3460_early_init(void *unused)
return;
}
/* Initialize the I2C controller before it is used. */
if (ptn_dev->bus && ptn_dev->bus->dev->ops && ptn_dev->bus->dev->ops->init)
ptn_dev->bus->dev->ops->init(ptn_dev->bus->dev);
if (ptn_dev->upstream && ptn_dev->upstream->dev->ops && ptn_dev->upstream->dev->ops->init)
ptn_dev->upstream->dev->ops->init(ptn_dev->upstream->dev);
ptn3460_init(ptn_dev);
}

2
src/drivers/intel/dptf/dptf.c
View file

@ -503,7 +503,7 @@ static void write_device_definitions(const struct device *dev)
enum dptf_participant p;
/* The CPU device gets an _ADR that matches the ACPI PCI address for 00:04.00 */
parent = dev && dev->bus ? dev->bus->dev : NULL;
parent = dev && dev->upstream ? dev->upstream->dev : NULL;
if (!parent || parent->path.type != DEVICE_PATH_PCI) {
printk(BIOS_ERR, "%s: DPTF objects must live under 00:04.0 PCI device\n",
__func__);

2
src/drivers/intel/ish/ish.c
View file

@ -12,7 +12,7 @@
static void ish_fill_ssdt_generator(const struct device *dev)
{
struct drivers_intel_ish_config *config = dev->chip_info;
struct device *root = dev->bus->dev;
struct device *root = dev->upstream->dev;
struct acpi_dp *dsd;
if (!config)

8
src/drivers/intel/mipi_camera/camera.c
View file

@ -199,7 +199,7 @@ static void camera_generate_pld(const struct device *dev)
static uint32_t address_for_dev_type(const struct device *dev, uint8_t dev_type)
{
struct drivers_intel_mipi_camera_config *config = dev->chip_info;
uint16_t i2c_bus = dev->bus ? dev->bus->secondary : 0xFFFF;
uint16_t i2c_bus = dev->upstream ? dev->upstream->secondary : 0xFFFF;
uint16_t i2c_addr;
switch (dev_type) {
@ -416,7 +416,7 @@ static void camera_fill_sensor(const struct device *dev)
.type = DEVICE_PATH_I2C,
.i2c.device = config->vcm_address,
};
struct device *vcm_dev = find_dev_path(dev->bus, &path);
struct device *vcm_dev = find_dev_path(dev->upstream, &path);
struct drivers_intel_mipi_camera_config *vcm_config;
vcm_config = vcm_dev ? vcm_dev->chip_info : NULL;
@ -927,7 +927,7 @@ static void camera_fill_ssdt(const struct device *dev)
const struct device *pdev;
if (config->has_power_resource) {
pdev = dev->bus->dev;
pdev = dev->upstream->dev;
if (!pdev || !pdev->enabled)
return;
@ -951,7 +951,7 @@ static void camera_fill_ssdt(const struct device *dev)
write_i2c_camera_device(dev, scope);
break;
case DEVICE_PATH_GENERIC:
pdev = dev->bus->dev;
pdev = dev->upstream->dev;
scope = acpi_device_scope(pdev);
if (!scope)
return;

2
src/drivers/intel/soundwire/soundwire.c
View file

@ -21,7 +21,7 @@ static bool link_enabled(const struct device *dev, unsigned int link)
{
struct device *child;
for (child = dev->link_list->children; child; child = child->sibling) {
for (child = dev->downstream->children; child; child = child->sibling) {
if (child->enabled && child->path.type == DEVICE_PATH_GENERIC &&
child->path.generic.id == link)
return true;

10
src/drivers/net/phy/m88e1512/m88e1512.c
View file

@ -21,10 +21,10 @@ static void m88e1512_init(struct device *dev)
if (config->downshift_cnt) {
if (config->downshift_cnt > DOWNSHIFT_CNT_MAX) {
printk(BIOS_INFO, "%s: Downshift counter for %s is too large.\n",
dev_path(dev->bus->dev), dev->chip_ops->name);
dev_path(dev->upstream->dev), dev->chip_ops->name);
} else {
printk(BIOS_DEBUG, "%s: Enable downshift after %d attempts for %s.\n",
dev_path(dev->bus->dev), config->downshift_cnt,
dev_path(dev->upstream->dev), config->downshift_cnt,
dev->chip_ops->name);
reg = mdio_read(dev, COPPER_SPEC_CTRL_REG_1);
@ -42,7 +42,7 @@ static void m88e1512_init(struct device *dev)
/* Configure LEDs if requested. */
if (config->configure_leds) {
printk(BIOS_DEBUG, "%s: Set a customized LED mode for %s.\n",
dev_path(dev->bus->dev), dev->chip_ops->name);
dev_path(dev->upstream->dev), dev->chip_ops->name);
/* Select page 3 to access LED function control register. */
switch_page(dev, 3);
@ -57,7 +57,7 @@ static void m88e1512_init(struct device *dev)
/* INTn can be routed to LED[2] pin. */
if (config->enable_int) {
printk(BIOS_DEBUG, "%s: INTn is routed to LED[2] pin %s.\n",
dev_path(dev->bus->dev), dev->chip_ops->name);
dev_path(dev->upstream->dev), dev->chip_ops->name);
/* Select page 3 to access LED function control register. */
switch_page(dev, 3);
@ -70,7 +70,7 @@ static void m88e1512_init(struct device *dev)
/* Set RGMII output impedance manually. */
if (config->force_mos) {
printk(BIOS_DEBUG, "%s: Set RGMII driver strength manually for %s.\n",
dev_path(dev->bus->dev), dev->chip_ops->name);
dev_path(dev->upstream->dev), dev->chip_ops->name);
/* Select page 2 to access RGMII output impedance calibration override
register. */

2
src/drivers/net/r8168.c
View file

@ -364,7 +364,7 @@ static void r8168_init(struct device *dev)
static void r8168_net_fill_ssdt(const struct device *dev)
{
struct drivers_net_config *config = dev->chip_info;
const char *path = acpi_device_path(dev->bus->dev);
const char *path = acpi_device_path(dev->upstream->dev);
u32 address;
if (!path || !config)

4
src/drivers/nxp/uwb/uwb.c
View file

@ -15,10 +15,10 @@ static int spi_acpi_get_bus(const struct device *dev)
struct device *spi_dev;
struct device_operations *ops;
if (!dev->bus || !dev->bus->dev)
if (!dev->upstream || !dev->upstream->dev)
return -1;
spi_dev = dev->bus->dev;
spi_dev = dev->upstream->dev;
ops = spi_dev->ops;
if (ops && ops->ops_spi_bus && ops->ops_spi_bus->dev_to_bus)

4
src/drivers/pcie/generic/generic.c
View file

@ -27,13 +27,13 @@ static void pcie_generic_fill_ssdt(const struct device *dev)
pci_rom_ssdt(dev);
config = dev->chip_info;
if (!config || !dev->bus || !dev->bus->dev)
if (!config || !dev->upstream || !dev->upstream->dev)
return;
const char *scope;
const char *name;
scope = acpi_device_path(dev->bus->dev);
scope = acpi_device_path(dev->upstream->dev);
name = acpi_device_name(dev);
acpigen_write_scope(scope);

4
src/drivers/spi/acpi/acpi.c
View file

@ -15,10 +15,10 @@ static int spi_acpi_get_bus(const struct device *dev)
struct device *spi_dev;
struct device_operations *ops;
if (!dev->bus || !dev->bus->dev)
if (!dev->upstream || !dev->upstream->dev)
return -1;
spi_dev = dev->bus->dev;
spi_dev = dev->upstream->dev;
ops = spi_dev->ops;
if (ops && ops->ops_spi_bus &&

2
src/drivers/usb/hub/acpi.c
View file

@ -41,7 +41,7 @@ static void usb_hub_add_ports(const struct device *dev)
struct device *port = NULL;
unsigned int child_count = 0;
while ((port = dev_bus_each_child(dev->link_list, port)) != NULL) {
while ((port = dev_bus_each_child(dev->downstream, port)) != NULL) {
if (child_count++ >= config->port_count) {
printk(BIOS_WARNING, "%s cannot be added. Port Count limit reached.\n",
dev_name(port));

2
src/drivers/usb/pci_xhci/pci_xhci.c
View file

@ -76,7 +76,7 @@ static const struct device *get_xhci_dev(const struct device *dev)
if (is_root_device(dev))
return NULL;
dev = dev->bus->dev;
dev = dev->upstream->dev;
}
return dev;

2
src/drivers/wifi/generic/acpi.c
View file

@ -610,7 +610,7 @@ void wifi_cnvi_fill_ssdt(const struct device *dev)
if (!dev)
return;
path = acpi_device_path(dev->bus->dev);
path = acpi_device_path(dev->upstream->dev);
if (!path)
return;

2
src/drivers/wifi/generic/smbios.c
View file

@ -38,5 +38,5 @@ int smbios_write_wifi_pcie(struct device *dev, int *handle, unsigned long *curre
int smbios_write_wifi_cnvi(struct device *dev, int *handle, unsigned long *current)
{
return smbios_write_wifi_pcie(dev->bus->dev, handle, current);
return smbios_write_wifi_pcie(dev->upstream->dev, handle, current);
}

2
src/drivers/wwan/fm/acpi_fm350gl.c
View file

@ -317,7 +317,7 @@ static void wwan_fm350gl_acpi_gpio_events(const struct device *dev)
static void wwan_fm350gl_acpi_fill_ssdt(const struct device *dev)
{
const struct drivers_wwan_fm_config *config = config_of(dev);
const struct device *parent = dev->bus->dev;
const struct device *parent = dev->upstream->dev;
const char *scope = acpi_device_path(parent);
const struct soc_intel_common_block_pcie_rtd3_config *rtd3_config;

2
src/ec/google/chromeec/ec_acpi.c
View file

@ -273,7 +273,7 @@ void google_chromeec_fill_ssdt_generator(const struct device *dev)
path.type = DEVICE_PATH_GENERIC;
path.generic.id = 0;
path.generic.subid = 0;
ec = alloc_find_dev(dev->bus, &path);
ec = alloc_find_dev(dev->upstream, &path);
ec->ops = &ec_ops;
if (CONFIG(DRIVERS_INTEL_DPTF))

13
src/include/device/device.h
View file

@ -95,8 +95,8 @@ struct bus {
*/
struct device {
DEVTREE_CONST struct bus *bus; /* bus this device is on, for bridge
* devices, it is the up stream bus */
DEVTREE_CONST struct bus *upstream;
DEVTREE_CONST struct bus *downstream;
DEVTREE_CONST struct device *sibling; /* next device on this bus */
@ -124,11 +124,6 @@ struct device {
/* Base registers for this device. I/O, MEM and Expansion ROM */
DEVTREE_CONST struct resource *resource_list;
/* links are (downstream) buses attached to the device, usually a leaf
* device with no children has 0 buses attached and a bridge has 1 bus
*/
DEVTREE_CONST struct bus *link_list;
#if !DEVTREE_EARLY
struct device_operations *ops;
struct chip_operations *chip_ops;
@ -458,11 +453,11 @@ static inline DEVTREE_CONST void *config_of(const struct device *dev)
static inline bool is_root_device(const struct device *dev)
{
if (!dev || !dev->bus)
if (!dev || !dev->upstream)
return false;
return (dev->path.type == DEVICE_PATH_ROOT) ||
(dev->bus->dev == dev);
(dev->upstream->dev == dev);
}
void enable_static_device(struct device *dev);

4
src/include/device/pci_ops.h
View file

@ -12,8 +12,8 @@ void __noreturn pcidev_die(void);
static __always_inline pci_devfn_t pcidev_bdf(const struct device *dev)
{
return (dev->path.pci.devfn << 12) | (dev->bus->secondary << 20) |
(dev->bus->segment_group << 28);
return (dev->path.pci.devfn << 12) | (dev->upstream->secondary << 20) |
(dev->upstream->segment_group << 28);
}
static __always_inline pci_devfn_t pcidev_assert(const struct device *dev)

8
src/lib/smbios.c
View file

@ -1114,8 +1114,8 @@ static int smbios_generate_type41_from_devtree(struct device *dev, int *handle,
return smbios_write_type41(current, handle,
name, // name
instance_id, // inst
dev->bus->segment_group, // segment group
dev->bus->secondary, //bus
dev->upstream->segment_group, // segment group
dev->upstream->secondary, //bus
PCI_SLOT(dev->path.pci.devfn), // device
PCI_FUNC(dev->path.pci.devfn), // func
device_type);
@ -1167,8 +1167,8 @@ static int smbios_generate_type9_from_devtree(struct device *dev, int *handle,
0,
1,
0,
dev->bus->segment_group,
dev->bus->secondary,
dev->upstream->segment_group,
dev->upstream->secondary,
dev->path.pci.devfn);
}

4
src/mainboard/aopen/dxplplusu/acpi_tables.c
View file

@ -11,7 +11,7 @@ unsigned long acpi_fill_madt(unsigned long current)
bdev = pcidev_on_root(2, 0);
/* P64H2 Bus B IOAPIC */
if (bdev)
dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(28, 0));
dev = pcidev_path_behind(bdev->downstream, PCI_DEVFN(28, 0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, res->base);
@ -19,7 +19,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* P64H2 Bus A IOAPIC */
if (bdev)
dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(30, 0));
dev = pcidev_path_behind(bdev->downstream, PCI_DEVFN(30, 0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, res->base);

2
src/mainboard/emulation/qemu-i440fx/northbridge.c
View file

@ -39,7 +39,7 @@ static void qemu_reserve_ports(struct device *dev, unsigned int idx,
static void cpu_pci_domain_set_resources(struct device *dev)
{
assign_resources(dev->link_list);
assign_resources(dev->downstream);
}
static void cpu_pci_domain_read_resources(struct device *dev)

4
src/mainboard/google/brox/mainboard.c
View file

@ -106,7 +106,7 @@ static void mainboard_dev_init(struct device *dev)
static void mainboard_generate_wwan_shutdown(const struct device *dev)
{
const struct drivers_wwan_fm_config *config = config_of(dev);
const struct device *parent = dev->bus->dev;
const struct device *parent = dev->upstream->dev;
if (!config)
return;
@ -126,7 +126,7 @@ static void mainboard_generate_wwan_shutdown(const struct device *dev)
static void mainboard_generate_dgpu_shutdown(const struct device *dev)
{
/* Call `_OFF` from the Power Resource associated with the dGPU's PEG port. */
const struct device *parent = dev->bus->dev;
const struct device *parent = dev->upstream->dev;
if (parent)
acpigen_emit_namestring(acpi_device_path_join(parent, "PGPR._OFF"));

4
src/mainboard/google/brya/mainboard.c
View file

@ -106,7 +106,7 @@ static void mainboard_dev_init(struct device *dev)
static void mainboard_generate_wwan_shutdown(const struct device *dev)
{
const struct drivers_wwan_fm_config *config = config_of(dev);
const struct device *parent = dev->bus->dev;
const struct device *parent = dev->upstream->dev;
if (!config)
return;
@ -126,7 +126,7 @@ static void mainboard_generate_wwan_shutdown(const struct device *dev)
static void mainboard_generate_dgpu_shutdown(const struct device *dev)
{
/* Call `_OFF` from the Power Resource associated with the dGPU's PEG port. */
const struct device *parent = dev->bus->dev;
const struct device *parent = dev->upstream->dev;
if (parent)
acpigen_emit_namestring(acpi_device_path_join(parent, "PGPR._OFF"));

2
src/mainboard/google/kahlee/variants/careena/mainboard.c
View file

@ -26,7 +26,7 @@ void variant_devtree_update(void)
if (mmio_dev == NULL)
return;
while ((child = dev_bus_each_child(mmio_dev->link_list, child)) != NULL) {
while ((child = dev_bus_each_child(mmio_dev->downstream, child)) != NULL) {
if (child->path.type != DEVICE_PATH_I2C)
continue;
if (child->path.i2c.device != 0x1a)

2
src/mainboard/google/kahlee/variants/treeya/audio.c
View file

@ -25,7 +25,7 @@ void variant_devtree_update(void)
}
} while (mmio_dev->path.mmio.addr != APU_I2C0_BASE);
while ((child = dev_bus_each_child(mmio_dev->link_list, child)) != NULL) {
while ((child = dev_bus_each_child(mmio_dev->downstream, child)) != NULL) {
if (child->path.type != DEVICE_PATH_I2C)
continue;
if (child->path.i2c.device != RT58_I2C_ADDRESS)

2
src/mainboard/google/octopus/mainboard.c
View file

@ -179,7 +179,7 @@ static void audio_codec_device_update(void)
{
struct device *audio_dev = NULL;
struct bus *audio_i2c_bus =
pcidev_path_on_root(PCH_DEVFN_I2C5)->link_list;
pcidev_path_on_root(PCH_DEVFN_I2C5)->downstream;
enum ssfc_audio_codec codec = ssfc_get_audio_codec();
while ((audio_dev = dev_bus_each_child(audio_i2c_bus, audio_dev))) {

2
src/mainboard/google/rex/mainboard.c
View file

@ -82,7 +82,7 @@ static void mainboard_generate_s0ix_hook(void)
static void mainboard_generate_wwan_shutdown(const struct device *dev)
{
const struct drivers_wwan_fm_config *config = config_of(dev);
const struct device *parent = dev->bus->dev;
const struct device *parent = dev->upstream->dev;
if (!config)
return;

2
src/mainboard/google/zork/variants/baseboard/ramstage_common.c
View file

@ -115,7 +115,7 @@ void variant_touchscreen_update(void)
if (variant_uses_v3_6_schematics())
return;
while ((child = dev_bus_each_child(mmio_dev->link_list, child)) != NULL) {
while ((child = dev_bus_each_child(mmio_dev->downstream, child)) != NULL) {
struct drivers_i2c_generic_config *cfg;
if (child->chip_ops == &drivers_i2c_generic_ops) {

4
src/mainboard/ibase/mb899/mptable.c
View file

@ -19,7 +19,7 @@ static void *smp_write_config_table(void *v)
firewire = dev_find_device(0x104c, 0x8023, 0);
if (firewire) {
firewire_bus = firewire->bus->secondary;
firewire_bus = firewire->upstream->secondary;
printk(BIOS_SPEW, "Firewire device is on bus %x\n",
firewire_bus);
}
@ -30,7 +30,7 @@ static void *smp_write_config_table(void *v)
if (!riser)
riser = dev_find_device(0x3388, 0x0022, 0);
if (riser) {
riser_bus = riser->link_list->secondary;
riser_bus = riser->downstream->secondary;
printk(BIOS_SPEW, "Riser bus is %x\n", riser_bus);
}

4
src/mainboard/kontron/986lcd-m/mptable.c
View file

@ -18,7 +18,7 @@ static void *smp_write_config_table(void *v)
firewire = dev_find_device(0x104c, 0x8023, 0);
if (firewire) {
firewire_bus = firewire->bus->secondary;
firewire_bus = firewire->upstream->secondary;
}
/* If a riser card is used, this riser is detected on bus 4, so its secondary bus is the */
@ -27,7 +27,7 @@ static void *smp_write_config_table(void *v)
if (!riser)
riser = dev_find_device(0x3388, 0x0022, 0);
if (riser) {
riser_bus = riser->link_list->secondary;
riser_bus = riser->downstream->secondary;
}
mptable_write_buses(mc, NULL, &isa_bus);

2
src/mainboard/pcengines/apu2/mainboard.c
View file

@ -277,7 +277,7 @@ const char *smbios_mainboard_serial_number(void)
dev = pcidev_on_root(2, 2);
if (dev)
dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0));
dev = pcidev_path_behind(dev->downstream, PCI_DEVFN(0, 0));
if (!dev)
return serial;

2
src/mainboard/roda/rk9/ti_pci7xx1.c
View file

@ -19,7 +19,7 @@ static void pci7xx1_enable(struct device *const dev)
u16 gcr = pci_read_config16(dev, 0x86);
for (fn = 5; fn > 0; --fn) {
const struct device *const d =
pcidev_path_behind(dev->bus, PCI_DEVFN(slot, fn));
pcidev_path_behind(dev->upstream, PCI_DEVFN(slot, fn));
if (!d || d->enabled) continue;
printk(BIOS_DEBUG,
"%s: Hiding function #%d.\n", __func__, fn);

6
src/mainboard/siemens/fa_ehl/mainboard.c
View file

@ -42,7 +42,7 @@ static uint8_t is_mac_adr_valid(uint8_t mac[MAC_ADDR_LEN])
*/
enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_LEN])
{
struct bus *parent = dev->bus;
struct bus *parent = dev->upstream;
uint8_t buf[16], mapping[16], i = 0, chain_len = 0;
memset(buf, 0, sizeof(buf));
@ -51,10 +51,10 @@ enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_L
/* The first entry in the tree is the device itself. */
buf[0] = dev->path.pci.devfn;
chain_len = 1;
for (i = 1; i < MAX_PATH_DEPTH && parent->dev->bus->subordinate; i++) {
for (i = 1; i < MAX_PATH_DEPTH && parent->dev->upstream->subordinate; i++) {
buf[i] = parent->dev->path.pci.devfn;
chain_len++;
parent = parent->dev->bus;
parent = parent->dev->upstream;
}
if (i == MAX_PATH_DEPTH) {
/* The path is deeper than MAX_PATH_DEPTH devices, error. */

6
src/mainboard/siemens/mc_apl1/mainboard.c
View file

@ -55,7 +55,7 @@ static uint8_t is_mac_adr_valid(uint8_t mac[MAC_ADDR_LEN])
*/
enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_LEN])
{
struct bus *parent = dev->bus;
struct bus *parent = dev->upstream;
uint8_t buf[16], mapping[16], i = 0, chain_len = 0;
memset(buf, 0, sizeof(buf));
@ -64,10 +64,10 @@ enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_L
/* The first entry in the tree is the device itself. */
buf[0] = dev->path.pci.devfn;
chain_len = 1;
for (i = 1; i < MAX_PATH_DEPTH && parent->dev->bus->subordinate; i++) {
for (i = 1; i < MAX_PATH_DEPTH && parent->dev->upstream->subordinate; i++) {
buf[i] = parent->dev->path.pci.devfn;
chain_len++;
parent = parent->dev->bus;
parent = parent->dev->upstream;
}
if (i == MAX_PATH_DEPTH) {
/* The path is deeper than MAX_PATH_DEPTH devices, error. */

4
src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
View file

@ -41,7 +41,7 @@ void variant_mainboard_final(void)
/* Disable clock outputs 0 and 2-4 (CLKOUT) for upstream XIO2001 PCIe to PCI
Bridge. */
struct device *parent = dev->bus->dev;
struct device *parent = dev->upstream->dev;
if (parent && parent->device == PCI_DID_TI_XIO2001)
pci_write_config8(parent, 0xd8, 0x1d);
}
@ -50,7 +50,7 @@ void variant_mainboard_final(void)
mainboard. */
dev = dev_find_device(PCI_VID_SIEMENS, 0x403f, 0);
if (dev) {
struct device *parent = dev->bus->dev;
struct device *parent = dev->upstream->dev;
if (parent && parent->device == PCI_DID_TI_XIO2001)
pci_write_config8(parent, 0xd8, 0x3c);
}

4
src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
View file

@ -51,7 +51,7 @@ void variant_mainboard_final(void)
/* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe to PCI
Bridge. */
struct device *parent = dev->bus->dev;
struct device *parent = dev->upstream->dev;
if (parent && parent->device == PCI_DID_TI_XIO2001)
pci_write_config8(parent, 0xd8, 0x0f);
}
@ -60,7 +60,7 @@ void variant_mainboard_final(void)
mainboard. */
dev = dev_find_device(PCI_VID_SIEMENS, 0x403f, 0);
if (dev) {
struct device *parent = dev->bus->dev;
struct device *parent = dev->upstream->dev;
if (parent && parent->device == PCI_DID_TI_XIO2001)
pci_write_config8(parent, 0xd8, 0x3e);
}

4
src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
View file

@ -41,7 +41,7 @@ void variant_mainboard_final(void)
/* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe to PCI
Bridge. */
struct device *parent = dev->bus->dev;
struct device *parent = dev->upstream->dev;
if (parent && parent->device == PCI_DID_TI_XIO2001)
pci_write_config8(parent, 0xd8, 0x0F);
}
@ -50,7 +50,7 @@ void variant_mainboard_final(void)
mainboard. */
dev = dev_find_device(PCI_VID_SIEMENS, 0x403f, 0);
if (dev) {
struct device *parent = dev->bus->dev;
struct device *parent = dev->upstream->dev;
if (parent && parent->device == PCI_DID_TI_XIO2001)
pci_write_config8(parent, 0xd8, 0x3c);
}

6
src/mainboard/siemens/mc_ehl/mainboard.c
View file

@ -42,7 +42,7 @@ static uint8_t is_mac_adr_valid(uint8_t mac[MAC_ADDR_LEN])
*/
enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_LEN])
{
struct bus *parent = dev->bus;
struct bus *parent = dev->upstream;
uint8_t buf[16], mapping[16], i = 0, chain_len = 0;
memset(buf, 0, sizeof(buf));
@ -51,10 +51,10 @@ enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_L
/* The first entry in the tree is the device itself. */
buf[0] = dev->path.pci.devfn;
chain_len = 1;
for (i = 1; i < MAX_PATH_DEPTH && parent->dev->bus->subordinate; i++) {
for (i = 1; i < MAX_PATH_DEPTH && parent->dev->upstream->subordinate; i++) {
buf[i] = parent->dev->path.pci.devfn;
chain_len++;
parent = parent->dev->bus;
parent = parent->dev->upstream;
}
if (i == MAX_PATH_DEPTH) {
/* The path is deeper than MAX_PATH_DEPTH devices, error. */

20
src/northbridge/amd/pi/00730F01/northbridge.c
View file

@ -186,7 +186,7 @@ static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *de
ivrs_ivhd_generic_t *ivhd_entry = (ivrs_ivhd_generic_t *)*current;
ivhd_entry->type = type;
ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8);
ivhd_entry->dev_id = dev->path.pci.devfn | (dev->upstream->secondary << 8);
ivhd_entry->dte_setting = data;
*current += sizeof(ivrs_ivhd_generic_t);
} else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) {
@ -195,12 +195,12 @@ static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *de
ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)*current;
ivhd_entry->type = type;
ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8);
ivhd_entry->dev_id = dev->path.pci.devfn | (dev->upstream->secondary << 8);
ivhd_entry->dte_setting = data;
ivhd_entry->reserved1 = 0;
ivhd_entry->reserved2 = 0;
ivhd_entry->source_dev_id = parent->path.pci.devfn |
(parent->bus->secondary << 8);
(parent->upstream->secondary << 8);
*current += sizeof(ivrs_ivhd_alias_t);
}
@ -243,7 +243,7 @@ static void add_ivhd_device_entries(struct device *parent, struct device *dev,
if (dev->path.type == DEVICE_PATH_PCI) {
if ((dev->bus->secondary == 0x0) &&
if ((dev->upstream->secondary == 0x0) &&
(dev->path.pci.devfn == 0x0))
*root_level = depth;
@ -253,8 +253,8 @@ static void add_ivhd_device_entries(struct device *parent, struct device *dev,
}
}
if (dev->link_list) {
for (sibling = dev->link_list->children; sibling; sibling = sibling->sibling)
if (dev->downstream) {
for (sibling = dev->downstream->children; sibling; sibling = sibling->sibling)
add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level,
current, ivhd_length);
}
@ -290,12 +290,12 @@ static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_t *ivrs_a
ivhd_11->flags = ivrs_agesa->ivhd.flags & 0x3f;
ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11);
/* BDF <bus>:00.2 */
ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8);
ivhd_11->device_id = 0x02 | (nb_dev->upstream->secondary << 8);
/* PCI Capability block 0x40 (type 0xf, "Secure device") */
ivhd_11->capability_offset = 0x40;
ivhd_11->iommu_base_low = ivrs_agesa->ivhd.iommu_base_low;
ivhd_11->iommu_base_high = ivrs_agesa->ivhd.iommu_base_high;
ivhd_11->pci_segment_group = nb_dev->bus->segment_group;
ivhd_11->pci_segment_group = nb_dev->upstream->segment_group;
ivhd_11->iommu_info = ivrs_agesa->ivhd.iommu_info;
ivhd_11->iommu_attributes.perf_counters =
(IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 7) & 0xf;
@ -358,12 +358,12 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
ivrs->ivhd.flags = ivrs_agesa->ivhd.flags;
ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd);
/* BDF <bus>:00.2 */
ivrs->ivhd.device_id = 0x02 | (nb_dev->bus->secondary << 8);
ivrs->ivhd.device_id = 0x02 | (nb_dev->upstream->secondary << 8);
/* PCI Capability block 0x40 (type 0xf, "Secure device") */
ivrs->ivhd.capability_offset = 0x40;
ivrs->ivhd.iommu_base_low = ivrs_agesa->ivhd.iommu_base_low;
ivrs->ivhd.iommu_base_high = ivrs_agesa->ivhd.iommu_base_high;
ivrs->ivhd.pci_segment_group = nb_dev->bus->segment_group;
ivrs->ivhd.pci_segment_group = nb_dev->upstream->segment_group;
ivrs->ivhd.iommu_info = ivrs_agesa->ivhd.iommu_info;
ivrs->ivhd.iommu_feature_info = ivrs_agesa->ivhd.iommu_feature_info;
/* Enable EFR if supported */

2
src/northbridge/intel/e7505/northbridge.c
View file

@ -52,7 +52,7 @@ static void mch_domain_read_resources(struct device *dev)
static void mch_domain_set_resources(struct device *dev)
{
assign_resources(dev->link_list);
assign_resources(dev->downstream);
}
struct device_operations e7505_pci_domain_ops = {

2
src/northbridge/intel/gm45/northbridge.c
View file

@ -122,7 +122,7 @@ static void mch_domain_set_resources(struct device *dev)
report_resource_stored(dev, resource, "");
}
assign_resources(dev->link_list);
assign_resources(dev->downstream);
}
static void mch_domain_init(struct device *dev)

10
src/northbridge/intel/haswell/pcie.c
View file

@ -20,8 +20,8 @@ static const char *pcie_acpi_name(const struct device *dev)
if (dev->path.type != DEVICE_PATH_PCI)
return NULL;
assert(dev->bus);
if (dev->bus->secondary == 0)
assert(dev->upstream);
if (dev->upstream->secondary == 0)
switch (dev->path.pci.devfn) {
case PCI_DEVFN(1, 0):
return "PEGP";
@ -31,12 +31,12 @@ static const char *pcie_acpi_name(const struct device *dev)
return "PEG2";
};
struct device *const port = dev->bus->dev;
struct device *const port = dev->upstream->dev;
assert(port);
assert(port->bus);
assert(port->upstream);
if (dev->path.pci.devfn == PCI_DEVFN(0, 0) &&
port->bus->secondary == 0 &&
port->upstream->secondary == 0 &&
(port->path.pci.devfn == PCI_DEVFN(1, 0) ||
port->path.pci.devfn == PCI_DEVFN(1, 1) ||
port->path.pci.devfn == PCI_DEVFN(1, 2)))

4
src/northbridge/intel/i440bx/northbridge.c
View file

@ -34,8 +34,8 @@ static void i440bx_domain_read_resources(struct device *dev)
pci_domain_read_resources(dev);
pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev->link_list->children;
pci_tolm = find_pci_tolm(dev->downstream);
mc_dev = dev->downstream->children;
if (mc_dev) {
unsigned long tomk, tolmk;
int idx;

4
src/northbridge/intel/i945/northbridge.c
View file

@ -26,7 +26,7 @@ static void mch_domain_read_resources(struct device *dev)
/* Can we find out how much memory we can use at most
* this way?
*/
pci_tolm = find_pci_tolm(dev->link_list);
pci_tolm = find_pci_tolm(dev->downstream);
printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm);
tolud = pci_read_config8(d0f0, TOLUD) << 24;
@ -65,7 +65,7 @@ static void mch_domain_set_resources(struct device *dev)
for (res = dev->resource_list; res; res = res->next)
report_resource_stored(dev, res, "");
assign_resources(dev->link_list);
assign_resources(dev->downstream);
}
static const char *northbridge_acpi_name(const struct device *dev)

2
src/northbridge/intel/pineview/northbridge.c
View file

@ -108,7 +108,7 @@ static void mch_domain_set_resources(struct device *dev)
for (res = dev->resource_list; res; res = res->next)
report_resource_stored(dev, res, "");
assign_resources(dev->link_list);
assign_resources(dev->downstream);
}
static void mch_domain_init(struct device *dev)

10
src/northbridge/intel/sandybridge/pcie.c
View file

@ -13,8 +13,8 @@ static const char *pcie_acpi_name(const struct device *dev)
if (dev->path.type != DEVICE_PATH_PCI)
return NULL;
assert(dev->bus);
if (dev->bus->secondary == 0)
assert(dev->upstream);
if (dev->upstream->secondary == 0)
switch (dev->path.pci.devfn) {
case PCI_DEVFN(1, 0):
return "PEGP";
@ -26,12 +26,12 @@ static const char *pcie_acpi_name(const struct device *dev)
return "PEG6";
};
struct device *const port = dev->bus->dev;
struct device *const port = dev->upstream->dev;
assert(port);
assert(port->bus);
assert(port->upstream);
if (dev->path.pci.devfn == PCI_DEVFN(0, 0) &&
port->bus->secondary == 0 &&
port->upstream->secondary == 0 &&
(port->path.pci.devfn == PCI_DEVFN(1, 0) ||
port->path.pci.devfn == PCI_DEVFN(1, 1) ||
port->path.pci.devfn == PCI_DEVFN(1, 2) ||

2
src/northbridge/intel/x4x/northbridge.c
View file

@ -72,7 +72,7 @@ static void mch_domain_set_resources(struct device *dev)
for (res = dev->resource_list; res; res = res->next)
report_resource_stored(dev, res, "");
assign_resources(dev->link_list);
assign_resources(dev->downstream);
}
static void mch_domain_init(struct device *dev)

4
src/soc/amd/cezanne/xhci.c
View file

@ -26,10 +26,10 @@ static const struct sci_source xhci_sci_sources[] = {
enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
{
if (dev->bus->dev->path.type != DEVICE_PATH_PCI)
if (dev->upstream->dev->path.type != DEVICE_PATH_PCI)
return CB_ERR_ARG;
if (dev->bus->dev->path.pci.devfn != PCIE_ABC_A_DEVFN)
if (dev->upstream->dev->path.pci.devfn != PCIE_ABC_A_DEVFN)
return CB_ERR_ARG;
if (dev->path.type != DEVICE_PATH_PCI)

44
src/soc/amd/common/block/acpi/ivrs.c
View file

@ -96,7 +96,7 @@ static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *de
memset(ivhd_entry, 0, sizeof(*ivhd_entry));
ivhd_entry->type = type;
ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8);
ivhd_entry->dev_id = dev->path.pci.devfn | (dev->upstream->secondary << 8);
ivhd_entry->dte_setting = data;
*current += sizeof(ivrs_ivhd_generic_t);
} else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) {
@ -104,12 +104,12 @@ static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *de
memset(ivhd_entry, 0, sizeof(*ivhd_entry));
ivhd_entry->type = type;
ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8);
ivhd_entry->dev_id = dev->path.pci.devfn | (dev->upstream->secondary << 8);
ivhd_entry->dte_setting = data;
ivhd_entry->reserved1 = 0;
ivhd_entry->reserved2 = 0;
ivhd_entry->source_dev_id = parent->path.pci.devfn |
(parent->bus->secondary << 8);
(parent->upstream->secondary << 8);
*current += sizeof(ivrs_ivhd_alias_t);
}
@ -145,7 +145,7 @@ static void add_ivhd_device_entries(struct device *parent, struct device *dev,
return;
if (dev->path.type == DEVICE_PATH_PCI) {
if ((dev->bus->secondary == nb_bus) &&
if ((dev->upstream->secondary == nb_bus) &&
(dev->path.pci.devfn == 0x0))
*root_level = depth;
@ -154,9 +154,9 @@ static void add_ivhd_device_entries(struct device *parent, struct device *dev,
ivrs_add_device_or_bridge(parent, dev, current);
}
if (!dev->link_list)
if (!dev->downstream)
return;
for (sibling = dev->link_list->children; sibling; sibling = sibling->sibling)
for (sibling = dev->downstream->children; sibling; sibling = sibling->sibling)
add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, current,
nb_bus);
}
@ -173,21 +173,21 @@ static unsigned long acpi_ivhd_misc(unsigned long current, struct device *dev)
* Add all possible PCI devices in the domain that can generate transactions
* processed by IOMMU. Start with device <bus>:01.0
*/
current = ivhd_dev_range(current, PCI_DEVFN(0, 3) | (dev->link_list->secondary << 8),
0xff | (dev->link_list->subordinate << 8), 0);
current = ivhd_dev_range(current, PCI_DEVFN(0, 3) | (dev->downstream->secondary << 8),
0xff | (dev->downstream->subordinate << 8), 0);
add_ivhd_device_entries(NULL, dev, 0, -1, &root_level,
&current, dev->link_list->secondary);
&current, dev->downstream->secondary);
res = probe_resource(dev, IOMMU_IOAPIC_IDX);
if (res) {
/* Describe IOAPIC associated with the IOMMU */
current = acpi_fill_ivrs_ioapic(current, (u8 *)(uintptr_t)res->base,
PCI_DEVFN(0, 1) | (dev->link_list->secondary << 8), 0);
PCI_DEVFN(0, 1) | (dev->downstream->secondary << 8), 0);
}
/* If the domain has secondary bus as zero then associate HPET & FCH IOAPIC */
if (dev->link_list->secondary == 0) {
if (dev->downstream->secondary == 0) {
/* Describe HPET */
current = ivhd_describe_hpet(current, 0x00, SMBUS_DEVFN);
/* Describe FCH IOAPICs */
@ -212,11 +212,11 @@ static unsigned long acpi_fill_ivrs40(unsigned long current, acpi_ivrs_ivhd_t *i
ivhd_40->flags = ivhd->flags & 0x3f;
ivhd_40->length = sizeof(struct acpi_ivrs_ivhd_40);
/* BDF <bus>:00.2 */
ivhd_40->device_id = 0x02 | (nb_dev->bus->secondary << 8);
ivhd_40->device_id = 0x02 | (nb_dev->upstream->secondary << 8);
ivhd_40->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID);
ivhd_40->iommu_base_low = ivhd->iommu_base_low;
ivhd_40->iommu_base_high = ivhd->iommu_base_high;
ivhd_40->pci_segment_group = nb_dev->bus->segment_group;
ivhd_40->pci_segment_group = nb_dev->upstream->segment_group;
ivhd_40->iommu_info = ivhd->iommu_info;
/* For type 40h bits 31:28 and 12:0 are reserved */
ivhd_40->iommu_attributes = ivhd->iommu_feature_info & 0xfffe000;
@ -230,9 +230,9 @@ static unsigned long acpi_fill_ivrs40(unsigned long current, acpi_ivrs_ivhd_t *i
/* Now repeat all the device entries from type 10h */
current_backup = current;
current = acpi_ivhd_misc(current, nb_dev->bus->dev);
current = acpi_ivhd_misc(current, nb_dev->upstream->dev);
if (nb_dev->bus->secondary == 0) {
if (nb_dev->upstream->secondary == 0) {
/* Describe EMMC */
if (CONFIG(SOC_AMD_COMMON_BLOCK_EMMC)) {
/* PCI_DEVFN(0x13, 1) doesn't exist in the hardware, but it's what the
@ -269,11 +269,11 @@ static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_ivhd_t *i
ivhd_11->flags = ivhd->flags & 0x3f;
ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11);
/* BDF <bus>:00.2 */
ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8);
ivhd_11->device_id = 0x02 | (nb_dev->upstream->secondary << 8);
ivhd_11->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID);
ivhd_11->iommu_base_low = ivhd->iommu_base_low;
ivhd_11->iommu_base_high = ivhd->iommu_base_high;
ivhd_11->pci_segment_group = nb_dev->bus->segment_group;
ivhd_11->pci_segment_group = nb_dev->upstream->segment_group;
ivhd_11->iommu_info = ivhd->iommu_info;
ivhd11_attr_ptr = (ivhd11_iommu_attr_t *)&ivhd->iommu_feature_info;
ivhd_11->iommu_attributes.perf_counters = ivhd11_attr_ptr->perf_counters;
@ -289,7 +289,7 @@ static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_ivhd_t *i
/* Now repeat all the device entries from type 10h */
current_backup = current;
current = acpi_ivhd_misc(current, nb_dev->bus->dev);
current = acpi_ivhd_misc(current, nb_dev->upstream->dev);
ivhd_11->length += (current - current_backup);
return acpi_fill_ivrs40(current, ivhd, nb_dev, iommu_dev);
@ -317,8 +317,8 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
while ((dev = dev_find_path(dev, DEVICE_PATH_DOMAIN)) != NULL) {
nb_dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0));
iommu_dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 2));
nb_dev = pcidev_path_behind(dev->downstream, PCI_DEVFN(0, 0));
iommu_dev = pcidev_path_behind(dev->downstream, PCI_DEVFN(0, 2));
if (!nb_dev) {
printk(BIOS_WARNING, "%s: Northbridge device not present!\n", __func__);
printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__);
@ -334,7 +334,7 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
ivhd->length = sizeof(struct acpi_ivrs_ivhd);
/* BDF <bus>:00.2 */
ivhd->device_id = 0x02 | (nb_dev->bus->secondary << 8);
ivhd->device_id = 0x02 | (nb_dev->upstream->secondary << 8);
ivhd->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID);
ivhd->iommu_base_low = pci_read_config32(iommu_dev, IOMMU_CAP_BASE_LO) & 0xffffc000;
ivhd->iommu_base_high = pci_read_config32(iommu_dev, IOMMU_CAP_BASE_HI);
@ -363,7 +363,7 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
ivhd->flags |= ((mmio_x18_value & MMIO_CTRL_HT_TUN_EN) ?
IVHD_FLAG_HT_TUN_EN : 0);
ivhd->pci_segment_group = nb_dev->bus->segment_group;
ivhd->pci_segment_group = nb_dev->upstream->segment_group;
ivhd->iommu_info = pci_read_config16(iommu_dev,
ivhd->capability_offset + 0x10) & 0x1F;

25
src/soc/amd/common/block/data_fabric/domain.c
View file

@ -34,12 +34,12 @@ void amd_pci_domain_scan_bus(struct device *domain)
limit = MIN(limit, PCI_BUSES_PER_SEGMENT_GROUP - 1);
/* Set bus first number of PCI root */
domain->link_list->secondary = bus;
domain->downstream->secondary = bus;
/* subordinate needs to be the same as secondary before pci_host_bridge_scan_bus call. */
domain->link_list->subordinate = bus;
domain->downstream->subordinate = bus;
/* Tell allocator about maximum PCI bus number in domain */
domain->link_list->max_subordinate = limit;
domain->link_list->segment_group = segment_group;
domain->downstream->max_subordinate = limit;
domain->downstream->segment_group = segment_group;
pci_host_bridge_scan_bus(domain);
}
@ -249,12 +249,12 @@ void amd_pci_domain_fill_ssdt(const struct device *domain)
/* PCI bus number range in domain */
printk(BIOS_DEBUG, "%s _CRS: adding busses [%x-%x] in segment group %x\n",
acpi_device_name(domain), domain->link_list->secondary,
domain->link_list->max_subordinate, domain->link_list->segment_group);
acpigen_resource_producer_bus_number(domain->link_list->secondary,
domain->link_list->max_subordinate);
acpi_device_name(domain), domain->downstream->secondary,
domain->downstream->max_subordinate, domain->downstream->segment_group);
acpigen_resource_producer_bus_number(domain->downstream->secondary,
domain->downstream->max_subordinate);
if (domain->link_list->secondary == 0 && domain->link_list->segment_group == 0) {
if (domain->downstream->secondary == 0 && domain->downstream->segment_group == 0) {
/* ACPI 6.4.2.5 I/O Port Descriptor */
acpigen_write_io16(PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_LAST_PORT, 1,
PCI_IO_CONFIG_PORT_COUNT, 1);
@ -282,7 +282,7 @@ void amd_pci_domain_fill_ssdt(const struct device *domain)
}
}
if (domain->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
if (domain->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
printk(BIOS_DEBUG, "%s _CRS: adding VGA resource\n", acpi_device_name(domain));
acpigen_resource_producer_mmio(VGA_MMIO_BASE, VGA_MMIO_LIMIT,
MEM_RSRC_FLAG_MEM_READ_WRITE | MEM_RSRC_FLAG_MEM_ATTR_CACHE);
@ -290,9 +290,8 @@ void amd_pci_domain_fill_ssdt(const struct device *domain)
acpigen_write_resourcetemplate_footer();
acpigen_write_SEG(domain->link_list->segment_group);
acpigen_write_BBN(domain->link_list->secondary);
acpigen_write_SEG(domain->downstream->segment_group);
acpigen_write_BBN(domain->downstream->secondary);
/* Scope */
acpigen_pop_len();
}

4
src/soc/amd/common/block/lpc/lpc.c
View file

@ -280,10 +280,10 @@ static void lpc_enable_children_resources(struct device *dev)
{
struct device *child;
if (!dev->link_list)
if (!dev->downstream)
return;
for (child = dev->link_list->children; child; child = child->sibling) {
for (child = dev->downstream->children; child; child = child->sibling) {
if (!child->enabled)
continue;
if (child->path.type != DEVICE_PATH_PNP)

4
src/soc/amd/genoa_poc/domain.c
View file

@ -18,7 +18,7 @@ static void genoa_domain_read_resources(struct device *domain)
amd_pci_domain_read_resources(domain);
// We only want to add the DRAM memory map once
if (domain->link_list->secondary == 0 && domain->link_list->segment_group == 0) {
if (domain->downstream->secondary == 0 && domain->downstream->segment_group == 0) {
/* 0x1000 is a large enough first index to be sure to not overlap with the
resources added by amd_pci_domain_read_resources */
add_opensil_memmap(domain, 0x1000);
@ -27,7 +27,7 @@ static void genoa_domain_read_resources(struct device *domain)
static void genoa_domain_set_resources(struct device *domain)
{
if (domain->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
if (domain->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
printk(BIOS_DEBUG, "Setting VGA decoding for domain 0x%x\n",
domain->path.domain.domain);
const union df_vga_en vga_en = {

6
src/soc/amd/glinda/xhci.c
View file

@ -34,13 +34,13 @@ static const struct sci_source xhci_sci_sources[] = {
enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
{
if (dev->bus->dev->path.type != DEVICE_PATH_PCI)
if (dev->upstream->dev->path.type != DEVICE_PATH_PCI)
return CB_ERR_ARG;
if (dev->path.type != DEVICE_PATH_PCI)
return CB_ERR_ARG;
if (dev->bus->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) {
if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) {
if (dev->path.pci.devfn == XHCI0_DEVFN) {
*gpe = xhci_sci_sources[0].gpe;
return CB_SUCCESS;
@ -48,7 +48,7 @@ enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
*gpe = xhci_sci_sources[1].gpe;
return CB_SUCCESS;
}
} else if (dev->bus->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) {
} else if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) {
if (dev->path.pci.devfn == XHCI2_DEVFN
&& dev->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2) {
*gpe = xhci_sci_sources[2].gpe;

6
src/soc/amd/mendocino/xhci.c
View file

@ -35,13 +35,13 @@ static const struct sci_source xhci_sci_sources[] = {
enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
{
if (dev->bus->dev->path.type != DEVICE_PATH_PCI)
if (dev->upstream->dev->path.type != DEVICE_PATH_PCI)
return CB_ERR_ARG;
if (dev->path.type != DEVICE_PATH_PCI)
return CB_ERR_ARG;
if (dev->bus->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) {
if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) {
if (dev->path.pci.devfn == XHCI0_DEVFN) {
*gpe = xhci_sci_sources[0].gpe;
return CB_SUCCESS;
@ -49,7 +49,7 @@ enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
*gpe = xhci_sci_sources[1].gpe;
return CB_SUCCESS;
}
} else if (dev->bus->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) {
} else if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) {
if (dev->path.pci.devfn == XHCI2_DEVFN
&& dev->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2) {
*gpe = xhci_sci_sources[2].gpe;

6
src/soc/amd/phoenix/xhci.c
View file

@ -39,13 +39,13 @@ static const struct sci_source xhci_sci_sources[] = {
enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
{
if (dev->bus->dev->path.type != DEVICE_PATH_PCI)
if (dev->upstream->dev->path.type != DEVICE_PATH_PCI)
return CB_ERR_ARG;
if (dev->path.type != DEVICE_PATH_PCI)
return CB_ERR_ARG;
if (dev->bus->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) {
if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) {
if (dev->path.pci.devfn == XHCI0_DEVFN) {
*gpe = xhci_sci_sources[0].gpe;
return CB_SUCCESS;
@ -55,7 +55,7 @@ enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
}
}
if (dev->bus->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) {
if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) {
if (dev->path.pci.devfn == USB4_XHCI0_DEVFN) {
*gpe = xhci_sci_sources[2].gpe;
return CB_SUCCESS;

4
src/soc/amd/picasso/xhci.c
View file

@ -26,10 +26,10 @@ static const struct sci_source xhci_sci_sources[] = {
enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
{
if (dev->bus->dev->path.type != DEVICE_PATH_PCI)
if (dev->upstream->dev->path.type != DEVICE_PATH_PCI)
return CB_ERR_ARG;
if (dev->bus->dev->path.pci.devfn != PCIE_GPP_A_DEVFN)
if (dev->upstream->dev->path.pci.devfn != PCIE_GPP_A_DEVFN)
return CB_ERR_ARG;
if (dev->path.type != DEVICE_PATH_PCI)

8
src/soc/amd/stoneyridge/northbridge.c
View file

@ -52,9 +52,9 @@ static void read_resources(struct device *dev)
static void create_vga_resource(struct device *dev)
{
if (!dev->link_list)
if (!dev->downstream)
return;
if (!(dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA))
if (!(dev->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA))
return;
printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev));
@ -67,8 +67,8 @@ static void set_resources(struct device *dev)
/* do we need this? */
create_vga_resource(dev);
if (dev->link_list && dev->link_list->children)
assign_resources(dev->link_list);
if (dev->downstream && dev->downstream->children)
assign_resources(dev->downstream);
}
static void northbridge_init(struct device *dev)

10
src/soc/cavium/cn81xx/ecam0.c
View file

@ -226,12 +226,12 @@ static void ecam0_init(struct device *dev)
* Search for missing devices on BUS 1.
* Only required for ARI capability programming.
*/
ecam0_fix_missing_devices(bridge->link_list);
ecam0_fix_missing_devices(bridge->downstream);
/* Program secure ARI capability on bus 1 */
child_last = NULL;
for (i = 0; i <= PCI_DEVFN(0x1f, 7); i++) {
child = pcidev_path_behind(bridge->link_list, i);
child = pcidev_path_behind(bridge->downstream, i);
if (!child || !child->enabled)
continue;
@ -250,7 +250,7 @@ static void ecam0_init(struct device *dev)
/* Program insecure ARI capability on bus 1 */
child_last = NULL;
for (i = 0; i <= PCI_DEVFN(0x1f, 7); i++) {
child = pcidev_path_behind(bridge->link_list, i);
child = pcidev_path_behind(bridge->downstream, i);
if (!child)
continue;
config = child->chip_info;
@ -281,7 +281,7 @@ static void ecam0_init(struct device *dev)
/* Enable / disable devices and functions on bus 1 */
for (i = 0; i <= PCI_DEVFN(0x1f, 7); i++) {
child = pcidev_path_behind(bridge->link_list, i);
child = pcidev_path_behind(bridge->downstream, i);
config = child ? child->chip_info : NULL;
if (child && child->enabled &&
((config && !config->secure) || !config))
@ -293,7 +293,7 @@ static void ecam0_init(struct device *dev)
/* Apply IRQ on PCI devices */
/* UUA */
for (i = 0; i < 4; i++) {
child = pcidev_path_behind(bridge->link_list,
child = pcidev_path_behind(bridge->downstream,
PCI_DEVFN(8, i));
if (!child)
continue;

2
src/soc/intel/apollolake/chip.c
View file

@ -478,7 +478,7 @@ static void parse_devicetree(FSP_S_CONFIG *silconfig)
return;
}
/* Only disable bus 0 devices. */
for (dev = dev->bus->children; dev; dev = dev->sibling) {
for (dev = dev->upstream->children; dev; dev = dev->sibling) {
if (!dev->enabled)
disable_dev(dev, silconfig);
}

4
src/soc/intel/braswell/southcluster.c
View file

@ -117,7 +117,7 @@ static void write_pci_config_irqs(void)
continue;
current_bdf = irq_dev->path.pci.devfn |
irq_dev->bus->secondary << 8;
irq_dev->upstream->secondary << 8;
/*
* Step 1: Get the INT_PIN and device structure to look for
@ -132,7 +132,7 @@ static void write_pci_config_irqs(void)
original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
parent_bdf = targ_dev->path.pci.devfn
| targ_dev->bus->secondary << 8;
| targ_dev->upstream->secondary << 8;
device_num = PCI_SLOT(parent_bdf);
if (ir->pcidev[device_num] == 0) {

2
src/soc/intel/common/block/acpi/pep.c
View file

@ -144,7 +144,7 @@ static enum acpi_device_sleep_states get_min_sleep_state(
case DEVICE_PATH_PCI:
/* skip external buses*/
if ((dev->bus->secondary != 0) || (!states_arr))
if ((dev->upstream->secondary != 0) || (!states_arr))
return ACPI_DEVICE_SLEEP_NONE;
for (size_t i = 0; i < size; i++)
if (states_arr[i].pci_dev == dev->path.pci.devfn)

4
src/soc/intel/common/block/lpc/lpc.c
View file

@ -102,10 +102,10 @@ static void pch_lpc_set_child_resources(struct device *dev)
{
struct device *child;
if (!dev->link_list)
if (!dev->downstream)
return;
for (child = dev->link_list->children; child; child = child->sibling)
for (child = dev->downstream->children; child; child = child->sibling)
pch_lpc_loop_resources(child);
}

6
src/soc/intel/common/block/pcie/rtd3/rtd3.c
View file

@ -140,7 +140,7 @@ pcie_rtd3_acpi_method_on(unsigned int pcie_rp,
enum pcie_rp_type rp_type,
const struct device *dev)
{
const struct device *parent = dev->bus->dev;
const struct device *parent = dev->upstream->dev;
acpigen_write_method_serialized("_ON", 0);
@ -224,7 +224,7 @@ pcie_rtd3_acpi_method_off(int pcie_rp,
const struct device *dev)
{
const struct device *parent = dev->bus->dev;
const struct device *parent = dev->upstream->dev;
acpigen_write_method_serialized("_OFF", 0);
@ -385,7 +385,7 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev)
const struct soc_intel_common_block_pcie_rtd3_config *config = config_of(dev);
static const char *const power_res_states[] = {"_PR0"};
const struct device *parent = dev->bus->dev;
const struct device *parent = dev->upstream->dev;
const char *scope = acpi_device_path(parent);
const struct opregion opregion = OPREGION("PXCS", PCI_CONFIG, 0, 0xff);
const struct fieldlist fieldlist[] = {

2
src/soc/intel/common/block/usb4/pcie.c
View file

@ -19,7 +19,7 @@ static void usb4_pcie_acpi_fill_ssdt(const struct device *dev)
int port_id;
/* Get parent PCI device */
parent = dev->bus->dev;
parent = dev->upstream->dev;
if (!parent) {
printk(BIOS_ERR, "%s: Unable to find parent device\n", __func__);
return;

4
src/soc/intel/common/block/xhci/xhci.c
View file

@ -92,8 +92,8 @@ void usb_xhci_disable_unused(bool (*ext_usb_xhci_en_cb)(unsigned int port_type,
return;
}
while ((hub = dev_bus_each_child(xhci->link_list, hub)) != NULL) {
while ((port = dev_bus_each_child(hub->link_list, port)) != NULL) {
while ((hub = dev_bus_each_child(xhci->downstream, hub)) != NULL) {
while ((port = dev_bus_each_child(hub->downstream, port)) != NULL) {
enable = true;
config = config_of(port);
if (config->type == UPC_TYPE_INTERNAL) {

4
src/soc/intel/denverton_ns/lpc.c
View file

@ -275,7 +275,7 @@ static u8 dnv_get_int_line(struct device *irq_dev)
/* Swizzle this device if needed */
config = targ_dev->chip_info;
parent_bdf = targ_dev->path.pci.devfn | targ_dev->bus->secondary << 8;
parent_bdf = targ_dev->path.pci.devfn | targ_dev->upstream->secondary << 8;
if (is_dnv_swizzled_rp(parent_bdf) && irq_dev != targ_dev) {
swiz_int_pin = dnv_get_swizzled_pin(config, parent_bdf, new_int_pin);
printk(BIOS_DEBUG, "%s: dnv swizzle %s from %c to %c\n", __func__,
@ -387,7 +387,7 @@ static void pch_pirq_init(struct device *dev)
int_line = dnv_get_int_line(irq_dev);
printk(BIOS_DEBUG, "%s: %02x:%02x.%d pin %d int line %d\n", __func__,
irq_dev->bus->secondary, devfn >> 3, devfn & 0x7, int_pin, int_line);
irq_dev->upstream->secondary, devfn >> 3, devfn & 0x7, int_pin, int_line);
pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
}

2
src/soc/intel/meteorlake/fsp_params.c
View file

@ -760,7 +760,7 @@ static void fill_fsps_pci_ssid_params(FSP_S_CONFIG *s_cfg,
for (dev = all_devices; dev; dev = dev->next) {
if (!(is_dev_enabled(dev) && dev->path.type == DEVICE_PATH_PCI &&
dev->bus->secondary == 0))
dev->upstream->secondary == 0))
continue;
if (dev->path.pci.devfn == PCI_DEVFN_ROOT) {

2
src/soc/intel/skylake/chip.c
View file

@ -94,7 +94,7 @@ const char *soc_acpi_name(const struct device *dev)
return NULL;
/* Match functions 0 and 1 for possible GPUs on a secondary bus */
if (dev->bus && dev->bus->secondary > 0) {
if (dev->upstream && dev->upstream->secondary > 0) {
switch (PCI_FUNC(dev->path.pci.devfn)) {
case 0: return "DEV0";
case 1: return "DEV1";

6
src/soc/intel/xeon_sp/chip_common.c
View file

@ -78,7 +78,7 @@ void iio_pci_domain_scan_bus(struct device *dev)
bus->max_subordinate = sr->BusLimit;
printk(BIOS_SPEW, "Scanning IIO stack %d: busses %x-%x\n", dev->path.domain.domain,
dev->link_list->secondary, dev->link_list->max_subordinate);
dev->downstream->secondary, dev->downstream->max_subordinate);
pci_host_bridge_scan_bus(dev);
}
@ -116,14 +116,14 @@ void attach_iio_stacks(struct device *dev)
if (!is_pcie_iio_stack_res(ri)) {
if (CONFIG(HAVE_IOAT_DOMAINS))
soc_create_ioat_domains(dn, dev->bus, ri);
soc_create_ioat_domains(dn, dev->upstream, ri);
continue;
}
struct device_path path;
path.type = DEVICE_PATH_DOMAIN;
path.domain.domain = dn.domain_path;
struct device *iio_domain = alloc_dev(dev->bus, &path);
struct device *iio_domain = alloc_dev(dev->upstream, &path);
if (iio_domain == NULL)
die("%s: out of memory.\n", __func__);
iio_domain->ops = &iio_pcie_domain_ops;

2
src/soc/intel/xeon_sp/cpx/soc_acpi.c
View file

@ -46,7 +46,7 @@ void uncore_fill_ssdt(const struct device *device)
struct iiostack_resource stack_info = {0};
/* Only add RTxx entries once. */
if (device->bus->secondary != 0 || device->bus->segment_group != 0)
if (device->upstream->secondary != 0 || device->upstream->segment_group != 0)
return;
get_iiostack_info(&stack_info);

2
src/soc/intel/xeon_sp/skx/soc_acpi.c
View file

@ -59,7 +59,7 @@ void uncore_fill_ssdt(const struct device *device)
const IIO_UDS *hob = get_iio_uds();
/* Only add RTxx entries once. */
if (device->bus->secondary != 0)
if (device->upstream->secondary != 0)
return;
for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; ++socket) {

4
src/soc/intel/xeon_sp/spr/soc_acpi.c
View file

@ -341,7 +341,7 @@ void uncore_fill_ssdt(const struct device *device)
bool stack_enabled;
/* Only add RTxx entries once. */
if (device->bus->secondary != 0)
if (device->upstream->secondary != 0)
return;
/*
@ -502,7 +502,7 @@ unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current)
for (cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC)
|| (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) {
|| (cpu->upstream->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) {
continue;
}
if (!cpu->enabled)

2
src/soc/intel/xeon_sp/uncore.c
View file

@ -192,7 +192,7 @@ static void mc_add_dram_resources(struct device *dev, int *res_count)
struct range_entry fsp_mem;
/* Only add dram resources once. */
if (dev->bus->secondary != 0 || dev->bus->segment_group != 0)
if (dev->upstream->secondary != 0 || dev->upstream->segment_group != 0)
return;
/* Read in the MAP registers and report their values. */

2
src/soc/intel/xeon_sp/uncore_acpi.c
View file

@ -225,7 +225,7 @@ static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current,
uint32_t pcie_seg,
bool is_atsr, bool *first)
{
const uint32_t bus = bridge_dev->bus->secondary;
const uint32_t bus = bridge_dev->upstream->secondary;
const uint32_t dev = PCI_SLOT(bridge_dev->path.pci.devfn);
const uint32_t func = PCI_FUNC(bridge_dev->path.pci.devfn);

4
src/southbridge/amd/pi/hudson/lpc.c
View file

@ -171,8 +171,8 @@ static void hudson_lpc_enable_childrens_resources(struct device *dev)
reg_var[0] = pci_read_config16(dev, 0x64);
struct device *child;
if (dev->link_list) {
for (child = dev->link_list->children; child; child = child->sibling) {
if (dev->downstream) {
for (child = dev->downstream->children; child; child = child->sibling) {
if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
struct resource *res;
for (res = child->resource_list; res; res = res->next) {

4
src/southbridge/intel/bd82x6x/pcie.c
View file

@ -145,8 +145,8 @@ static void pch_pcie_pm_early(struct device *dev)
* must be a static device from devicetree.cb.
* If one is found assume it's an integrated device and not a PCIe slot.
*/
if (dev->link_list)
child = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0));
if (dev->downstream)
child = pcidev_path_behind(dev->downstream, PCI_DEVFN(0, 0));
/* Set slot power limit as configured above */
reg32 = pci_read_config32(dev, cap + PCI_EXP_SLTCAP);

12
src/superio/common/generic.c
View file

@ -13,8 +13,8 @@ static void generic_set_resources(struct device *dev)
if (!dev)
return;
if (dev->link_list)
assign_resources(dev->link_list);
if (dev->downstream)
assign_resources(dev->downstream);
for (res = dev->resource_list; res; res = res->next) {
if (!(res->flags & IORESOURCE_ASSIGNED))
@ -159,8 +159,8 @@ static void generic_ssdt(const struct device *dev)
acpigen_write_acquire(mutex, 0xffff);
/* Pick one of the children as the generic SIO doesn't have config mode */
if (dev->link_list && dev->link_list->children)
pnp_ssdt_enter_conf_mode(dev->link_list->children, "^INDX", "^DATA");
if (dev->downstream && dev->downstream->children)
pnp_ssdt_enter_conf_mode(dev->downstream->children, "^INDX", "^DATA");
/* Backup LDN */
acpigen_write_store();
@ -178,8 +178,8 @@ static void generic_ssdt(const struct device *dev)
acpigen_emit_namestring("^LDN");
/* Pick one of the children as the generic SIO doesn't have config mode */
if (dev->link_list && dev->link_list->children)
pnp_ssdt_exit_conf_mode(dev->link_list->children, "^INDX", "^DATA");
if (dev->downstream && dev->downstream->children)
pnp_ssdt_exit_conf_mode(dev->downstream->children, "^INDX", "^DATA");
acpigen_write_release(mutex);
}

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