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mb/google/nissa/var/craask: Add GTCH7503 and split TS by SSFC 

Add G2 touchscreen GTCH7503 for craaskino.
Use SSFC to separate touchscreen settings.

Bit 38-41 for TS_SOURCE:
(1) TS_UNPROVISIONED  -->  0
(2) TS_GTCH7503       -->  1

BUG=b:277979947
TEST=(1) emerge-nissa coreboot
     (2) Test on craaskino with G2 touchscreen
     (3) Test on craaskino with elan touchscreen

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I636f21be39f26a617653e134129a11479e801ea2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
This commit is contained in:
Tyler Wang 2023-04-11 11:19:38 +08:00 committed by Eric Lai
parent 2cf25eb74b
commit 7fd0c59969
2 changed files with 27 additions and 2 deletions
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1
src/mainboard/google/brya/Kconfig.name
View File

@ -237,6 +237,7 @@ config BOARD_GOOGLE_CRAASK
select DRIVERS_INTEL_MIPI_CAMERA
select HAVE_WWAN_POWER_SEQUENCE
select CHROMEOS_WIFI_SAR if CHROMEOS
select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
config BOARD_GOOGLE_OSIRIS
bool "-> Osiris"

28
src/mainboard/google/brya/variants/craask/overridetree.cb
View File

@ -31,6 +31,10 @@ fw_config
option CODEC_ALC5682I_VS 0
option CODEC_NAU8825 1
end
field TS_SOURCE 38 41
option TS_UNPROVISIONED 0
option TS_GTCH7503 1
end
end
chip soc/intel/alderlake
@ -322,7 +326,25 @@ chip soc/intel/alderlake
register "generic.enable_delay_ms" = "12"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 0x40 on end
device i2c 0x40 on
probe TS_SOURCE TS_UNPROVISIONED
end
end
chip drivers/i2c/hid
register "generic.hid" = ""GTCH7503""
register "generic.desc" = ""G2 Touchscreen""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
register "generic.probed" = "1"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
register "generic.reset_delay_ms" = "120"
register "generic.reset_off_delay_ms" = "3"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
register "generic.enable_delay_ms" = "12"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 0x40 on
probe TS_SOURCE TS_GTCH7503
end
end
chip drivers/generic/gpio_keys
register "name" = ""PENH""
@ -353,7 +375,9 @@ chip soc/intel/alderlake
register "generic.enable_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 10 on end
device i2c 10 on
probe TS_SOURCE TS_UNPROVISIONED
end
end
end
device ref i2c2 on