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mb/google/brya/var/primus: Update thermal table for primus 

- Add 4 TEMP_SENSORs
- Configure granularity of power limits

BUG=b:200836803
TEST=USE="project_primus emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Ariel_Fang <ariel_fang@wistron.corp-partner.google.com>
Change-Id: Id4d8dbe678b7f0870aeffa0a0118e65de9d5c22d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit is contained in:
Ariel_Fang 2021-11-11 17:49:40 +08:00 committed by Felix Held
parent 3e8ca37b6c
commit 7fe266d59d
1 changed files with 14 additions and 7 deletions
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21
src/mainboard/google/brya/variants/primus/overridetree.cb
View File

@ -78,21 +78,28 @@ chip soc/intel/alderlake
device ref dtt on device ref dtt on
chip drivers/intel/dptf chip drivers/intel/dptf
## sensor information ## sensor information
register "options.tsr[0].desc" = ""DRAM"" register "options.tsr[0].desc" = ""SSD""
register "options.tsr[1].desc" = ""Charger"" register "options.tsr[1].desc" = ""CHARGER""
register "options.tsr[2].desc" = ""MEMORY""
register "options.tsr[3].desc" = ""TYPEC""
# TODO: below values are initial reference values only
## Passive Policy ## Passive Policy
register "policies.passive" = "{ register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 5000),
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 90, 5000),
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 90, 5000),
[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 5000),
}" }"
## Critical Policy ## Critical Policy
register "policies.critical" = "{ register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 89, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
}" }"
register "controls.power_limits" = "{ register "controls.power_limits" = "{
@ -101,7 +108,7 @@ chip soc/intel/alderlake
.max_power = 15000, .max_power = 15000,
.time_window_min = 28 * MSECS_PER_SEC, .time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200, .granularity = 250,
}, },
.pl2 = { .pl2 = {
.min_power = 55000, .min_power = 55000,