soc/intel/jasperlake: Enable FSP-S compression

Use LZ4 compression technique to compress FSP-S. This provides some
SPI ROM space savings(~60 KiB) in each CBFS. FSP-M is XIP and hence not
compressed. LZ4 is chosen over LZMA since the decompression saves
~50 ms for an extra overhead of ~1.5 KiB.

LZ4 Compression:
fsps.bin	0xa9fc0	fsp	203423 LZ4  (262144 decompressed)
LZ4 Decompression:
 17:starting LZ4 decompress (ignore for x86)          433,550 (1,154)
 18:finished LZ4 decompress (ignore for x86)          461,620 (28,069)

LZMA Compression:
fsps.bin	0xa9fc0	fsp	202132 LZMA (262144 decompressed)
LZMA Decompression:
 15:starting LZMA decompress (ignore for x86)         478,448 (1,174)
 16:finished LZMA decompress (ignore for x86)         557,725 (79,277)

BUG=b:158034451
TEST=Build and boot waddledoo mainboard.

Change-Id: I416b1d91d7f4836b1e9c641b0fe07b39876364ba
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Karthikeyan Ramasubramanian 2020-06-16 23:54:46 -06:00 committed by Patrick Georgi
parent 203af60464
commit 8021b474fb
1 changed files with 1 additions and 0 deletions

View File

@ -17,6 +17,7 @@ config CPU_SPECIFIC_OPTIONS
select CACHE_MRC_SETTINGS
select CPU_INTEL_COMMON
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select FSP_COMPRESS_FSP_S_LZ4
select FSP_M_XIP
select GENERIC_GPIO_LIB
select HAVE_FSP_GOP