nb/intel/x4x: Remove apic 0 from devicetree
This is added at runtime. Change-Id: I7716f8a972e2280179aa6aee00488b22413c0c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69298 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
parent
98c92570d9
commit
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on
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ops x4x_cpu_bus_ops # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
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device domain 0 on
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ops x4x_pci_domain_ops # PCI domain
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subsystemid 0x8086 0x0028 inherit
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on
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ops x4x_cpu_bus_ops # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
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device domain 0 on
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ops x4x_pci_domain_ops # PCI domain
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subsystemid 0x1458 0x5000 inherit
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on
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ops x4x_cpu_bus_ops # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
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device domain 0 on
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ops x4x_pci_domain_ops # PCI domain
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subsystemid 0x1458 0x5000 inherit
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on
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ops x4x_cpu_bus_ops # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
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device domain 0 on
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ops x4x_pci_domain_ops # PCI domain
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subsystemid 0x1458 0x5000 inherit
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on
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ops x4x_cpu_bus_ops # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
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device domain 0 on
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ops x4x_pci_domain_ops # PCI domain
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subsystemid 0x1458 0x5000 inherit
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@ -1,12 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on
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ops x4x_cpu_bus_ops # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
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device domain 0 on
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ops x4x_pci_domain_ops # PCI domain
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subsystemid 0x1458 0x5000 inherit
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on
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ops x4x_cpu_bus_ops # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
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device domain 0 on
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ops x4x_pci_domain_ops # PCI domain
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device pci 0.0 on end # Host Bridge
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@ -1,12 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on
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ops x4x_cpu_bus_ops # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
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device domain 0 on
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ops x4x_pci_domain_ops # PCI domain
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device pci 0.0 on end # Host Bridge
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@ -1,12 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on
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ops x4x_cpu_bus_ops # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
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device domain 0 on
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ops x4x_pci_domain_ops # PCI domain
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device pci 0.0 on end # Host Bridge
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on
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ops x4x_cpu_bus_ops # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
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device domain 0 on
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ops x4x_pci_domain_ops # PCI domain
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device pci 0.0 on end # Host Bridge
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@ -1,12 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on
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ops x4x_cpu_bus_ops # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
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device domain 0 on
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ops x4x_pci_domain_ops # PCI domain
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device pci 0.0 on end # Host Bridge
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@ -1,12 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on
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ops x4x_cpu_bus_ops # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
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device domain 0 on
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ops x4x_pci_domain_ops # PCI domain
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device pci 0.0 on # Host Bridge
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on
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ops x4x_cpu_bus_ops # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
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device domain 0 on
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ops x4x_pci_domain_ops # PCI domain
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device pci 0.0 on end # Host Bridge
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@ -1,12 +1,7 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on
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ops x4x_cpu_bus_ops # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
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device domain 0 on
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ops x4x_pci_domain_ops # PCI domain
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device pci 0.0 on end # Host Bridge
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@ -1,12 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on
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ops x4x_cpu_bus_ops # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
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device domain 0 on
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ops x4x_pci_domain_ops # PCI domain
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subsystemid 0x1458 0x5000 inherit
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@ -1,12 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on
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ops x4x_cpu_bus_ops # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
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device domain 0 on
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ops x4x_pci_domain_ops # PCI domain
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subsystemid 0x1458 0x5000 inherit
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@ -1,12 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on
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ops x4x_cpu_bus_ops # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
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device domain 0 on
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ops x4x_pci_domain_ops # PCI domain
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subsystemid 0x8086 0x0028 inherit
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on
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ops x4x_cpu_bus_ops # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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end
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device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
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device domain 0 on
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ops x4x_pci_domain_ops # PCI domain
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subsystemid 0x17aa 0x304f inherit
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