From 803241c03e4987d5039c2aa4babcf8b3718f559f Mon Sep 17 00:00:00 2001 From: Elyes Haouas Date: Sat, 8 Oct 2022 15:50:32 +0200 Subject: [PATCH] device/dram/ddr2: Use 'enum cb_err' instead of 'int' Signed-off-by: Elyes Haouas Change-Id: I8ea6e773d858b30d75ff93d4fe07301f3825c1cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/68240 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/device/dram/ddr2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 2cacc853c9..ce7a3bf777 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -122,7 +122,7 @@ u8 spd_get_msbs(u8 c) * Decodes a raw SPD data from a DDR2 DIMM. * Returns cycle time in 1/256th ns. */ -static int spd_decode_tck_time(u32 *tck, u8 c) +static enum cb_err spd_decode_tck_time(u32 *tck, u8 c) { u8 high, low; @@ -159,7 +159,7 @@ static int spd_decode_tck_time(u32 *tck, u8 c) * Decodes a raw SPD data from a DDR2 DIMM. * Returns cycle time in 1/256th ns. */ -static int spd_decode_bcd_time(u32 *bcd, u8 c) +static enum cb_err spd_decode_bcd_time(u32 *bcd, u8 c) { u8 high, low; @@ -194,7 +194,7 @@ static u32 spd_decode_quarter_time(u8 c) * Decodes a raw SPD data from a DDR2 DIMM. * Returns cycle time in 1/256th us. */ -static int spd_decode_tRR_time(u32 *tRR, u8 c) +static enum cb_err spd_decode_tRR_time(u32 *tRR, u8 c) { switch (c & ~0x80) { default: