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soc/amd/stoneyridge: Fix GPIO bank1 control definition 

Change-Id: Ia6c7357ba0c581dc46d173f462efce181847a4e1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20526
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marshall Dawson 2017-07-10 18:26:28 -06:00 committed by Martin Roth
parent 5ebc8652cc
commit 8040fbf9fb
1 changed files with 1 additions and 1 deletions
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2
src/soc/amd/stoneyridge/include/soc/gpio.h
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@ -58,7 +58,7 @@
#define GPIO_42 (GPIO_BANK0_CONTROL + 0xa8) #define GPIO_42 (GPIO_BANK0_CONTROL + 0xa8)
/* GPIO_64 - GPIO_127 */ /* GPIO_64 - GPIO_127 */
#define GPIO_BANK1 (CONTROL AMD_SB_ACPI_MMIO_ADDR + 0x1600) #define GPIO_BANK1_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x1600)
#define GPIO_64 (GPIO_BANK1_CONTROL + 0x00) #define GPIO_64 (GPIO_BANK1_CONTROL + 0x00)
#define GPIO_65 (GPIO_BANK1_CONTROL + 0x04) #define GPIO_65 (GPIO_BANK1_CONTROL + 0x04)
#define GPIO_66 (GPIO_BANK1_CONTROL + 0x08) #define GPIO_66 (GPIO_BANK1_CONTROL + 0x08)