mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDur

This patch updates the SLP_Sx assertion widths and power cycle duration
for volteer.

Power cycle duration:
With default value,
     S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0

With value set to 1,
     S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0

BUG=b:159108661
TEST=Verified that the power cycle duration is 1~2s with a global reset
on volteer.

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Idf4e0c3a60b4ac59e31df1357f2ff28f195ff17f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>

src/mainboard/google/volteer/variants/baseboard/devicetree.cb

@@ -154,6 +154,40 @@ chip soc/intel/tigerlake
 		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
 	}"
 
+	# Set the minimum assertion width
+	# PchPmSlpS3MinAssert:
+	#	- 1: 60us
+	#	- 2: 1ms
+	#	- 3: 50ms
+	#	- 4: 2s
+	register "PchPmSlpS3MinAssert"  = "3"  # 50ms
+	# PchPmSlpS4MinAssert:
+	#	- 1 = 1s
+	#	- 2 = 2s
+	#	- 3 = 3s
+	#	- 4 = 4s
+	register "PchPmSlpS4MinAssert"  = "1"  # 1s
+	# PchPmSlpSusMinAssert:
+	#	- 1 = 0ms
+	#	- 2 = 500ms
+	#	- 3 = 1s
+	#	- 4 = 4s
+	register "PchPmSlpSusMinAssert" = "3"  # 1s
+	# PchPmSlpAMinAssert
+	#	- 1 = 0ms
+	#	- 2 = 4s
+	#	- 3 = 98ms
+	#	- 4 = 2s
+	register "PchPmSlpAMinAssert"   = "3"  # 98ms
+
+	# NOTE: Duration programmed in the below register should never be smaller than the
+	# stretch duration programmed in the following registers -
+	#	- GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
+	#	- GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
+	#	- PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
+	#	- PM_CFG.SLP_LAN_MIN_ASST_WDTH
+	register "PchPmPwrCycDur" = "1"       # 1s
+
 	# HD Audio
 	register "PchHdaDspEnable" = "1"
 	register "PchHdaAudioLinkHdaEnable" = "0"