mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in Noibat

BUG=b:160296662
BRANCH=none
TEST=none

Change-Id: I5298e1779461995a98722099b397692351767089
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42975
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Edward O'Callaghan 2020-07-01 18:49:13 +10:00 committed by Edward O'Callaghan
parent dc7b94450f
commit 8056c910bc
1 changed files with 10 additions and 0 deletions

View File

@ -74,6 +74,16 @@ chip soc/intel/cannonlake
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0
register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Type-A Port 4 register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Type-A Port 4
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(6)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(5)"
# Enable eMMC HS400 # Enable eMMC HS400
register "ScsEmmcHs400Enabled" = "1" register "ScsEmmcHs400Enabled" = "1"