soc/intel/cnl: Use Kconfig to disable HECI1

This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Cannon Lake
and ensures disable_heci1() is guarded against this config.

Also, makes dt CSE PCI device `on` by default.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Idd57d2713fe83de5fb93e399734414ca99977d0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/mainboard/google/drallion/variants/drallion/devicetree.cb

@@ -411,7 +411,7 @@ chip soc/intel/cannonlake
 		end # I2C #1
 		device pci 15.2 off end # I2C #2
 		device pci 15.3 off end # I2C #3
-		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R
 		device pci 16.3 off end # Management Engine KT Redirection

src/mainboard/google/hatch/variants/baseboard/devicetree.cb

@@ -296,7 +296,7 @@ chip soc/intel/cannonlake
 		device pci 15.1 on  end # I2C #1
 		device pci 15.2 on  end # I2C #2
 		device pci 15.3 on  end # I2C #3
-		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R
 		device pci 16.3 off end # Management Engine KT Redirection

src/mainboard/google/sarien/variants/arcada/devicetree.cb

@@ -342,7 +342,7 @@ chip soc/intel/cannonlake
 		end # I2C #1
 		device pci 15.2 off end # I2C #2
 		device pci 15.3 off end # I2C #3
-		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R
 		device pci 16.3 off end # Management Engine KT Redirection

src/mainboard/google/sarien/variants/sarien/devicetree.cb

@@ -363,7 +363,7 @@ chip soc/intel/cannonlake
 		end # I2C #1
 		device pci 15.2 off end # I2C #2
 		device pci 15.3 off end # I2C #3
-		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R
 		device pci 16.3 off end # Management Engine KT Redirection

src/soc/intel/cannonlake/Kconfig

@@ -107,6 +107,9 @@ config CPU_SPECIFIC_OPTIONS
 	select UDELAY_TSC
 	select UDK_2017_BINDING
 
+config DISABLE_HECI1_AT_PRE_BOOT
+	default y if MAINBOARD_HAS_CHROMEOS
+
 config MAX_CPUS
 	int
 	default 12

src/soc/intel/cannonlake/fsp_params.c

@@ -587,7 +587,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 
 	params->Heci3Enabled = is_devfn_enabled(PCH_DEVFN_CSE_3);
 #if !CONFIG(HECI_DISABLE_USING_SMM)
-	params->Heci1Disabled = !is_devfn_enabled(PCH_DEVFN_CSE);
+	params->Heci1Disabled = CONFIG(DISABLE_HECI1_AT_PRE_BOOT);
 #endif
 	params->Device4Enable = config->Device4Enable;
 

src/soc/intel/cannonlake/smihandler.c

@@ -16,10 +16,7 @@
  */
 void smihandler_soc_at_finalize(void)
 {
-	if (!CONFIG(HECI_DISABLE_USING_SMM))
+	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM))
-		return;
-
-	if (!is_devfn_enabled(PCH_DEVFN_CSE))
 		heci_disable();
 }