mb/google/dedede: do UART pad config at board-level
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I5482f44b361925b7d2dbcbf1065c1be035c68b0b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49424 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -3,7 +3,7 @@
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#include <baseboard/variants.h>
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#include <baseboard/variants.h>
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#include <bootblock_common.h>
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#include <bootblock_common.h>
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void bootblock_mainboard_init(void)
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void bootblock_mainboard_early_init(void)
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{
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{
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const struct pad_config *pads;
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const struct pad_config *pads;
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size_t num;
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size_t num;
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@ -407,6 +407,11 @@ static const struct pad_config early_gpio_table[] = {
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/* C5 : RAM_STRAP_3 */
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/* C5 : RAM_STRAP_3 */
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PAD_CFG_GPI(GPP_C5, NONE, DEEP),
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PAD_CFG_GPI(GPP_C5, NONE, DEEP),
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/* C20 : UART2 RX */
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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/* C21 : UART2 TX */
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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/* D1 : WLAN_PERST_L */
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/* D1 : WLAN_PERST_L */
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PAD_CFG_GPO(GPP_D1, 1, DEEP),
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PAD_CFG_GPO(GPP_D1, 1, DEEP),
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