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mb/google/hatch/variants/helios: Modify DPTF parameters 

Modify DTRT CPU Throttle Effect on TSR0 change to TSR3.

BUG=b:131272830
BRANCH=firmware-hatch-12672.B
TEST=emerge-hatch coreboot chromeos-bootimage

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I5b4645d7552e795a33c1b86d95c4061da71c65bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38299
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kane Chen 2020-01-09 14:25:01 +08:00 committed by Nico Huber
parent 834d8c2998
commit 805da6ba53
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl
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@ -99,8 +99,8 @@ Name (DART, Package () {
}) })
Name (DTRT, Package () { Name (DTRT, Package () {
/* CPU Throttle Effect on TSR0 */ /* CPU Throttle Effect on TSR3 */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR3, 100, 60, 0, 0, 0, 0 },
/* Charger Throttle Effect on TSR0 */ /* Charger Throttle Effect on TSR0 */
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 },