Applying 11_26_car_tyan.diff from Yinghai Lu.

NOTE: This will break the tree so it can be fixed up later



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/arch/i386/init/ldscript.lb

@@ -27,7 +27,9 @@
 OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
 OUTPUT_ARCH(i386)
 
+/*
 ENTRY(_start)
+*/
 
 TARGET(binary)
 INPUT(linuxbios_ram.rom)
@@ -41,6 +43,8 @@ SECTIONS
 		_eram = . ;
 	}
 
+	. = _ROMBASE + ROM_IMAGE_SIZE - 0x10000;
+
 	/* This section might be better named .setup */
 	.rom . : {
 		_rom = .;

src/cpu/amd/car/cache_as_ram.inc

@@ -9,19 +9,20 @@
 	/* Save the BIST result */
 	movl    %eax, %ebp
 	
-	// for normal part %ebx already contain cpu_init_detected from fallback call
+	/*for normal part %ebx already contain cpu_init_detected from fallback call */
 
-CacheAsRam:
+cache_as_ram_setup:
 	/* hope we can skip the double set for normal part */
 #if USE_FALLBACK_IMAGE == 1
 
+	/* check if cpu_init_detected */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
 	andl $0x00000800, %eax
-	movl %eax, %ebx ;  // We store the status about if cpu_init_detected
+	movl %eax, %ebx  /* We store the status */
 	
 	/* Set MtrrFixDramModEn for clear fixed mtrr */
-	xorl	%eax, %eax			# clear %eax and %edx
+	xorl	%eax, %eax			
 	xorl	%edx, %edx			
 
 enable_fixed_mtrr_dram_modify:
@@ -97,13 +98,16 @@ clear_fixed_var_mtrr_out:
         xorl    %edx, %edx
         movl    $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
         wrmsr
-#else
+#endif /*  USE_FALLBACK_IMAGE == 1*/
+
+#if USE_FALLBACK_IMAGE == 0
+
         /* disable cache */
         movl    %cr0, %eax
         orl    $(0x1<<30),%eax
         movl    %eax, %cr0
 
-#endif /*  USE_FALLBACK_IMAGE == 1*/
+#endif 
 
 #if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
         /* enable write base caching so we can do execute in place
@@ -151,7 +155,7 @@ clear_fixed_var_mtrr_out:
 	movl	%esp, %ebp
 	pushl %ebx  /* init detected */
 	pushl %eax  /* bist */
-	call    amd64_main
+	call    cache_as_ram_main
 	/* We will not go back */
 
 fixed_mtrr_msr: 
@@ -169,4 +173,4 @@ var_iorr_msr:
 mem_top:
         .long   0xC001001A, 0xC001001D
         .long   0x000 /* NULL, end of table */
-.CacheAsRam_out:
+cache_as_ram_setup_out:

src/cpu/amd/car/post_cache_as_ram.c

@@ -1,3 +1,19 @@
+
+#include "cpu/amd/car/disable_cache_as_ram.c"
+
+#include "cpu/amd/car/clear_1m_ram.c"
+
+static inline void print_debug_pcar(const char *strval, uint32_t val)
+{
+#if CONFIG_USE_INIT
+        printk_debug("%s%08x\r\n", strval, val);
+#else
+        print_debug(strval); print_debug_hex32(val); print_debug("\r\n");
+#endif
+}
+
+
+
 static void post_cache_as_ram(unsigned cpu_reset)
 {
 
@@ -10,19 +26,11 @@ static void post_cache_as_ram(unsigned cpu_reset)
                 "movl   %%esp, %0\n\t"
                 : "=a" (v_esp)
         );
-#if CONFIG_USE_INIT
+        print_debug_pcar("v_esp=", v_esp);
-        printk_debug("v_esp=%08x\r\n", v_esp);
-#else
-        print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
-#endif
         }
 #endif
 
-#if CONFIG_USE_INIT
+        print_debug_pcar("cpu_reset = ",cpu_reset);
-        printk_debug("cpu_reset = %08x\r\n",cpu_reset);
-#else
-        print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
-#endif
 
         if(cpu_reset == 0) {
                 print_debug("Clearing initial memory region: ");
@@ -35,12 +43,19 @@ static void post_cache_as_ram(unsigned cpu_reset)
                 ::"a" (cpu_reset)
         );
 
-#include "cpu/amd/car/disable_cache_as_ram.c"
+	disable_cache_as_ram();
 
         if(cpu_reset==0) { // cpu_reset don't need to clear it 
-#include "cpu/amd/car/clear_1m_ram.c"
+		clear_1m_ram();
         }
 
+#if 0
+	int i;
+	for(i=0;i<0x800000;i++) {
+		outb(0x66, 0x80);
+	}
+#endif
+
         __asm__ volatile (
                 /* set new esp */ /* before _RAMBASE */
                 "subl   %0, %%ebp\n\t"
@@ -58,6 +73,7 @@ static void post_cache_as_ram(unsigned cpu_reset)
                 );
 
                 print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
+
                 if(new_cpu_reset==0) {
                         print_debug("done\r\n");
                 } else
@@ -65,11 +81,9 @@ static void post_cache_as_ram(unsigned cpu_reset)
                         print_debug("\r\n");
                 }
 
-#if CONFIG_USE_INIT
+                print_debug_pcar("new_cpu_reset = ", new_cpu_reset);
-                printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
+
-#else
+
-                print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
-#endif
                 /*copy and execute linuxbios_ram */
                 copy_and_run(new_cpu_reset);
                 /* We will not return */

src/cpu/amd/dualcore/dualcore_id.c

@@ -24,7 +24,7 @@ static inline struct node_core_id get_node_core_id(unsigned nb_cfg_54) {
 	struct node_core_id id;
 	//    get the apicid via cpuid(1) ebx[27:24]
 	if( nb_cfg_54) {
-                //   when NB_CFG[54] is set, nodid = ebx[27:25], coreid = ebx[24]
+                //   when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24]
                 id.coreid = (cpuid_ebx(1) >> 24) & 0xf;
                 id.nodeid = (id.coreid>>1);
                 id.coreid &= 1;

src/cpu/amd/model_fxx/init_cpus.c

@@ -1,75 +1,256 @@
 //it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID
-static unsigned init_cpus(unsigned cpu_init_detectedx, int controllers, const struct mem_controller *ctrl)
+
+typedef void (*process_ap_t)(unsigned apicid, void *gp);
+
+static void for_each_ap(unsigned bsp_apicid, unsigned core0_only, process_ap_t process_ap, void *gp)
 {
-		unsigned cpu_reset;
+	// here assume the OS don't change our apicid
-		unsigned bsp_apicid = 0;
+	unsigned ap_apicid;
-                struct node_core_id id;
 
-	#if CONFIG_LOGICAL_CPUS == 1
+	unsigned nodes;
-		/* if dual core is not enabled, we don't need reorder the apicid */
+        unsigned siblings = 0;
-                set_apicid_cpuid_lo();
+        unsigned disable_siblings;
-	#endif	
+        unsigned e0_later_single_core;
+        unsigned nb_cfg_54;
+        int i,j;
 
-                id = get_node_core_id_x(); // that is initid
+	/* get_nodes define in in_coherent_ht.c */
-        #if ENABLE_APIC_EXT_ID == 1
+	nodes = get_nodes();
-                if(id.coreid == 0) {
+
-                        enable_apic_ext_id(id.nodeid);
+        disable_siblings = !CONFIG_LOGICAL_CPUS;
+#if CONFIG_LOGICAL_CPUS == 1
+        if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // 0 mean dual core
+                disable_siblings = 1;
+        }
+#endif
+
+	/* here I assume that all node are same stepping, otherwise we can use use nb_cfg_54 from bsp for all nodes */
+        nb_cfg_54 = read_nb_cfg_54();
+
+
+        for(i=0; i<nodes;i++) {
+		e0_later_single_core = 0;
+                j = ((pci_read_config32(PCI_DEV(0, 0x18+i, 3), 0xe8) >> 12) & 3);
+                if(nb_cfg_54) {
+ 	               if(j == 0 ){ // if it is single core, we need to increase siblings for apic calculation 
+        	               e0_later_single_core = is_e0_later_in_bsp(i);  // single core
+                       } 
+                       if(e0_later_single_core) {
+                                j=1;
+                       }
                 }
-        #endif
+                siblings = j;
+
+		unsigned jj;
+
+		if(e0_later_single_core || disable_siblings || core0_only) {
+			jj = 0;
+		} else {
+			jj = siblings;
+		}	
+		
+	
+                for(j=0; j<=jj; j++) {
+
+                        ap_apicid = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
 
                 #if (ENABLE_APIC_EXT_ID == 1)
-	                #if LIFT_BSP_APIC_ID == 1
+			#if LIFT_BSP_APIC_ID == 0
-                        bsp_apicid += APIC_ID_OFFSET;
+			if( (i!=0) || (j!=0)) /* except bsp */
-			#endif	
+			#endif
-		#endif
+                        	ap_apicid += APIC_ID_OFFSET;
+                #endif
+
+			if(ap_apicid == bsp_apicid) continue;
+
+			process_ap(ap_apicid, gp); 
+
+                }
+        }
+}
 
 
-                enable_lapic();
+static inline int lapic_remote_read(int apicid, int reg, unsigned *pvalue)
+{
+        int timeout;
+        unsigned status;
+        int result;
+        lapic_wait_icr_idle();
+        lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
+        lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
+        timeout = 0;
 
-		init_timer(); 
+        do {
+                status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
+        } while (status == LAPIC_ICR_BUSY && timeout++ < 1000);
 
+        timeout = 0;
+        do {
+                status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
+        } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
+
+        result = -1;
+        if (status == LAPIC_ICR_RR_VALID) {
+                *pvalue = lapic_read(LAPIC_RRR);
+                result = 0;
+        }
+        return result;
+}
+
+#define LAPIC_MSG_REG 0x380
+
+
+static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id, const char *str)
+{
+	#if CONFIG_USE_INIT == 0
+		print_debug(str);
+        	print_debug(" ---- {APICID = "); print_debug_hex8(apicid);
+		print_debug(" NODEID = "), print_debug_hex8(id.nodeid); print_debug(" COREID = "), print_debug_hex8(id.coreid);
+	        print_debug("} --- \r\n");
+        #else
+                printk_debug("%s --- {  APICID = %02x NODEID = %02x COREID = %02x} ---\r\n", str, apicid, id.nodeid, id.coreid);
+        #endif
+}
+
+
+static void wait_cpu_state(unsigned apicid, unsigned state)
+{
+        unsigned readback;
+	int loop =100000;
+        while(--loop>0) {
+                if(lapic_remote_read(apicid, LAPIC_MSG_REG, &readback)!=0) continue;
+                if((readback & 0xff) == state) break; //target cpu is in stage started
+        }
+}
+
+static void wait_ap_started(unsigned ap_apicid, void *gp )
+{
+        wait_cpu_state(ap_apicid, 0x33); // started
+}
+
+static void wait_all_aps_started(unsigned bsp_apicid)
+{
+        for_each_ap(bsp_apicid, 0 , wait_ap_started, (void *)0);
+}
+
+static void allow_all_aps_stop(unsigned bsp_apicid)
+{
+        lapic_write(LAPIC_MSG_REG, (bsp_apicid<<24) | 0x44); // allow aps to stop
+}
+
+
+static unsigned init_cpus(unsigned cpu_init_detectedx)
+{
+		unsigned bsp_apicid = 0;
+		unsigned apicid;
+                struct node_core_id id;
+
+		/* 
+                 * already set early mtrr in cache_as_ram.inc
+		 */
+
+		/* that is from initial apicid, we need nodeid and coreid later */
+		id = get_node_core_id_x(); 
+
+
+                /* NB_CFG MSR is shared between cores, so we need make sure core0 is done at first --- use wait_all_core0_started  */
+		if(id.coreid == 0) {
+                	set_apicid_cpuid_lo(); /* only set it on core0 */
+			#if ENABLE_APIC_EXT_ID == 1
+                        enable_apic_ext_id(id.nodeid);
+			#endif
+                }
+
+		enable_lapic();
+//              init_timer(); // We need TMICT to pass msg for FID/VID change
 
         #if (ENABLE_APIC_EXT_ID == 1)
-            #if LIFT_BSP_APIC_ID == 0
+		unsigned initial_apicid = get_initial_apicid();	
-                if( id.nodeid != 0 ) //all except cores in node0
+                #if LIFT_BSP_APIC_ID == 0
-            #endif
+                if( initial_apicid != 0 ) // other than bsp
-			{
+                #endif
-				//get initial apic id and lift it
+                {
-				uint32_t dword = lapic_read(LAPIC_ID);
+                                /* use initial apic id to lift it */
-				dword &= ~(0xff<<24);
+                                uint32_t dword = lapic_read(LAPIC_ID);
-				dword |= ((get_initial_apicid() + APIC_ID_OFFSET)<<24);
+                                dword &= ~(0xff<<24);
-	                        lapic_write(LAPIC_ID, dword );
+                                dword |= (((initial_apicid + APIC_ID_OFFSET) & 0xff)<<24);
-			}
+
+                                lapic_write(LAPIC_ID, dword);
+                }
+
+                #if LIFT_BSP_APIC_ID == 1
+                bsp_apicid += APIC_ID_OFFSET;
+                #endif
+
         #endif
 
-                if (cpu_init_detectedx) {
+		/* get the apicid, it may be lifted already */
-//                       __asm__ volatile ("jmp __cpu_reset");
+		apicid = lapicid();
-                        soft_reset(); //  avoid soft reset? , I don't want to reinit ram again, make sure bsp get get INIT, So need to send one INIT to BSP ....
-                                        /*
-                                                1. check if it is BSP
-                                                2. if not send INIT to BSP and get out
-                                                3. if it is BSP, check if the mem is inited or not
-                                                4. if not inited, issue soft reset
-                                                5. if it is inited, call post_cache_as_ram with cpu_reset ==0. --- need to clear first 1M ram
-                                        */
 
-#if 0
+#if 1 
-                        if(!mem_inited(controllers, ctrl)) {
+		// show our apicid, nodeid, and coreid
-                                print_debug("mem is not initialized properly, need to hard reset\r\n");
+		if( id.coreid==0 ) {
-                                hard_reset();
+			if (id.nodeid!=0) //all core0 except bsp
-                        }
+				print_apicid_nodeid_coreid(apicid, id, " core0: ");
-                        cpu_reset = 1;
+		}
-                        post_cache_as_ram(cpu_reset);
+	#if 1 
-#endif
+                else { //all core1
-                        //no return;
+			print_apicid_nodeid_coreid(apicid, id, " core1: ");
                 }
-                distinguish_cpu_resets(id.nodeid);
+	#endif
 
-                if (!boot_cpu()) {
+#endif
-                        // We need stop the CACHE as RAM for this CPU too
+
-                        #include "cpu/amd/car/disable_cache_as_ram.c"
+                if (cpu_init_detectedx) {
-                        stop_this_cpu(); // it will stop all cores except core0 of cpu0
+			print_apicid_nodeid_coreid(apicid, id, "\r\n\r\n\r\nINIT detect from ");
+
+			print_debug("\r\nIssuing SOFT_RESET...\r\n");
+
+			soft_reset();
+
+                }
+
+		if(id.coreid==0) {
+	                distinguish_cpu_resets(id.nodeid);
+	//              start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set
+		}
+
+		//here don't need to wait 
+		lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x33); // mark the cpu is started
+
+		if(apicid != bsp_apicid) {
+                        // We need to stop the CACHE as RAM for this CPU, really?
+			wait_cpu_state(bsp_apicid, 0x44);
+			lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu
+
+			disable_cache_as_ram(); // inline
+                        stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp .... 
                 }
 
 		return bsp_apicid;
 }
+
+#if CONFIG_LOGICAL_CPUS == 1
+
+static unsigned is_core0_started(unsigned nodeid)
+{
+        uint32_t htic;
+        device_t device;
+        device = PCI_DEV(0, 0x18 + nodeid, 0);
+        htic = pci_read_config32(device, HT_INIT_CONTROL);
+        htic &= HTIC_INIT_Detect;
+        return htic;
+}
+
+static void wait_all_core0_started(void)
+{
+	//When core0 is started, it will distingush_cpu_resets. So wait for that
+	unsigned i;
+	unsigned nodes = get_nodes();
+
+	for(i=1;i<nodes;i++) { // skip bsp, because it is running on bsp
+		while(!is_core0_started(i)) {}
+	}
+}
+
+#endif

src/cpu/amd/model_fxx/node_id.c

@@ -1,12 +0,0 @@
-/* 2004.12 yhlu add dual core support */
-
-#include <arch/cpu.h>
-#include "cpu/amd/model_fxx/model_fxx_msr.h"
-
-static inline unsigned get_node_id(void) {
-	unsigned nodeid;
-	//    get the apicid via cpuid(1) ebx[27:24]
-        nodeid = (cpuid_ebx(1) >> 24) & 0x7;
-	return nodeid;
-}
-

src/mainboard/tyan/s2850/Config.lb

@@ -93,9 +93,13 @@ end
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
+
 if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds

src/mainboard/tyan/s2850/cache_as_ram_auto.c

@@ -14,7 +14,6 @@
 #include "ram/ramtest.c"
 
 #include "northbridge/amd/amdk8/cpu_rev.c"
-#define K8_HT_FREQ_1G_SUPPORT 0
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
@@ -36,27 +35,6 @@
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
 
 static void hard_reset(void)
 {
@@ -123,50 +101,28 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
-#include "cpu/amd/dualcore/dualcore.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
 #endif
+#include "cpu/amd/dualcore/dualcore.c"
 
 #include "cpu/amd/car/copy_and_run.c"
 
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+
 #if USE_FALLBACK_IMAGE == 1
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-void real_main(unsigned long bist);
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-
-void amd64_main(unsigned long bist)
 {
-#if CONFIG_LOGICAL_CPUS==1
+        unsigned last_boot_normal_x = last_boot_normal();
-        struct node_core_id id;
-#else
-        unsigned nodeid;
-#endif
-        /* Make cerain my local apic is useable */
-//        enable_lapic();
 
-#if CONFIG_LOGICAL_CPUS==1
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        id = get_node_core_id_x();
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
-        /* Is this a cpu only reset? */
+                if (last_boot_normal_x) {
-        if (cpu_init_detected(id.nodeid)) {
-#else
-//        nodeid = lapicid();
-	nodeid = get_node_id();
-        /* Is this a cpu only reset? */
-        if (cpu_init_detected(nodeid)) {
-#endif
-                if (last_boot_normal()) {
-                        goto normal_image;
-                } else {
-                        goto cpu_reset;
-                }
-        }
-
-        /* Is this a secondary cpu? */
-        if (!boot_cpu()) {
-                if (last_boot_normal()) {
                         goto normal_image;
                 } else {
                         goto fallback_image;
@@ -178,11 +134,10 @@ void amd64_main(unsigned long bist)
 
         enumerate_ht_chain();
 
-        /* Setup the ck804 */
         amd8111_enable_rom();
 
         /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal()) {
+        if (bios_reset_detected() && last_boot_normal_x) {
                 goto normal_image;
         }
         /* This is the primary cpu how should I boot? */
@@ -195,24 +150,27 @@ void amd64_main(unsigned long bist)
  normal_image:
         __asm__ volatile ("jmp __normal_image"
                 : /* outputs */
-                : "a" (bist) /* inputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
                 );
- cpu_reset:
-#if 0
-        //CPU reset will reset memtroller ???
-        asm volatile ("jmp __cpu_reset" 
-                : /* outputs */ 
-                : "a"(bist) /* inputs */
-                );
-#endif
 
  fallback_image:
-        real_main(bist);
+	;
 }
-void real_main(unsigned long bist)
-#else
-void amd64_main(unsigned long bist)
 #endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+
+#if USE_FALLBACK_IMAGE == 1
+        failover_process(bist, cpu_init_detectedx);
+#endif
+        real_main(bist, cpu_init_detectedx);
+
+}
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const struct mem_controller cpu[] = {
 		{
@@ -230,51 +188,7 @@ void amd64_main(unsigned long bist)
 	unsigned cpu_reset = 0;
 
         if (bist == 0) {
-#if CONFIG_LOGICAL_CPUS==1
+		init_cpus(cpu_init_detectedx);
-        	struct node_core_id id;
-#else
-	        unsigned nodeid;
-#endif
-                /* Skip this if there was a built in self test failure */
-//                amd_early_mtrr_init(); # don't need, already done in cache_as_ram
-
-#if CONFIG_LOGICAL_CPUS==1
-                set_apicid_cpuid_lo();
-		id = get_node_core_id_x(); // that is initid
-#else
-                nodeid = get_node_id();
-#endif
-
-                enable_lapic();
-                init_timer();
-
-
-#if CONFIG_LOGICAL_CPUS==1
-                if(id.coreid == 0) {
-                        if (cpu_init_detected(id.nodeid)) {
-				cpu_reset = 1;
-				goto cpu_reset_x;
-                        }
-                        distinguish_cpu_resets(id.nodeid);
-                }
-#else
-                if (cpu_init_detected(nodeid)) {
-			cpu_reset = 1;
-			goto cpu_reset_x;
-                }
-                distinguish_cpu_resets(nodeid);
-#endif
-
-
-                if (!boot_cpu()
-#if CONFIG_LOGICAL_CPUS==1 
-                        || (id.coreid != 0)
-#endif
-                ) {
-			// We need stop the CACHE as RAM for this CPU too
-			#include "cpu/amd/car/cache_as_ram_post.c"
-                        stop_this_cpu(); // it will stop all cores except core0 of cpu0
-                }
         }
 
 	
@@ -297,6 +211,7 @@ void amd64_main(unsigned long bist)
         // It is said that we should start core1 after all core0 launched
         start_other_cores();
 #endif
+        // automatically set that for you, but you might meet tight space
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
@@ -309,90 +224,5 @@ void amd64_main(unsigned long bist)
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
-
+	post_cache_as_ram(cpu_reset);
-#if 1
-        {
-        /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
-        unsigned v_esp;
-        __asm__ volatile (
-                "movl   %%esp, %0\n\t"
-                : "=a" (v_esp)
-        );
-#if CONFIG_USE_INIT
-        printk_debug("v_esp=%08x\r\n", v_esp);
-#else           
-        print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
-#endif    
-        }
-#endif
-
-#if 1
-
-
-cpu_reset_x:
-
-#if CONFIG_USE_INIT
-        printk_debug("cpu_reset = %08x\r\n",cpu_reset);
-#else
-        print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
-#endif
-
-	if(cpu_reset == 0) {
-	        print_debug("Clearing initial memory region: ");
-	}
-	print_debug("No cache as ram now - ");
-
-	/* store cpu_reset to ebx */
-        __asm__ volatile (
-                "movl %0, %%ebx\n\t"
-                ::"a" (cpu_reset)
-        );
-
-	if(cpu_reset==0) {
-#define CLEAR_FIRST_1M_RAM 1
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-	else {
-#undef CLEAR_FIRST_1M_RAM 
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-
-	__asm__ volatile (
-                /* set new esp */ /* before _RAMBASE */
-                "subl   %0, %%ebp\n\t"
-                "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
-	);
-
-	{
-		unsigned new_cpu_reset;
-
-		/* get back cpu_reset from ebx */
-		__asm__ volatile (
-			"movl %%ebx, %0\n\t"
-			:"=a" (new_cpu_reset)
-		);
-
-		print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
-		if(new_cpu_reset==0) {        
-		        print_debug("done\r\n");	
-		} else 
-		{	
-			print_debug("\r\n");
-		}
-
-#if CONFIG_USE_INIT
-                printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
-#else
-                print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
-#endif
-		/*copy and execute linuxbios_ram */
-		copy_and_run(new_cpu_reset);
-		/* We will not return */
-	}
-#endif
-
-
-	print_debug("should not be here -\r\n");
-
 }

src/mainboard/tyan/s2875/Config.lb

@@ -93,9 +93,13 @@ end
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
+
 if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds

src/mainboard/tyan/s2875/Options.lb

@@ -52,7 +52,7 @@ uses OBJCOPY
 uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses K8_E0_MEM_HOLE_SIZEK
+uses K8_HW_MEM_HOLE_SIZEK
 
 uses USE_DCACHE_RAM
 uses DCACHE_RAM_BASE
@@ -71,7 +71,10 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=131072
+#256K
+default FALLBACK_SIZE=0x40000
+
 
 ##
 ## Build code for the fallback boot
@@ -120,7 +123,7 @@ default CONFIG_LOGICAL_CPUS=1
 default CONFIG_CHIP_NAME=1
 
 #1G memory hole
-default K8_E0_MEM_HOLE_SIZEK=0x100000
+default K8_HW_MEM_HOLE_SIZEK=0x100000
 
 #VGA Console
 default CONFIG_CONSOLE_VGA=1
@@ -130,10 +133,10 @@ default CONFIG_PCI_ROM_RUN=1
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=0
+default USE_DCACHE_RAM=1
 default DCACHE_RAM_BASE=0xcf000
 default DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
+default CONFIG_USE_INIT=1
 
 ##
 ## Build code to setup a generic IOAPIC

src/mainboard/tyan/s2875/cache_as_ram_auto.c

@@ -14,7 +14,6 @@
 #include "ram/ramtest.c"
 
 #include "northbridge/amd/amdk8/cpu_rev.c"
-#define K8_HT_FREQ_1G_SUPPORT 0
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
@@ -37,27 +36,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
 
 static void hard_reset(void)
 {
@@ -124,54 +102,29 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
-#include "cpu/amd/dualcore/dualcore.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
 #endif
-
+#include "cpu/amd/dualcore/dualcore.c"
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 
 #include "cpu/amd/car/copy_and_run.c"
 
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+
 #if USE_FALLBACK_IMAGE == 1
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-void real_main(unsigned long bist);
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-
-void amd64_main(unsigned long bist)
 {
-#if CONFIG_LOGICAL_CPUS==1
-        struct node_core_id id;
-#else
-        unsigned nodeid;
-#endif
-        /* Make cerain my local apic is useable */
-//        enable_lapic();
 
-#if CONFIG_LOGICAL_CPUS==1
+        unsigned last_boot_normal_x = last_boot_normal();
-        id = get_node_core_id_x();
-        /* Is this a cpu only reset? */
-        if (cpu_init_detected(id.nodeid)) {
-#else
-//        nodeid = lapicid();
-	nodeid = get_node_id();
-        /* Is this a cpu only reset? */
-        if (cpu_init_detected(nodeid)) {
-#endif
-                if (last_boot_normal()) {
-                        goto normal_image;
-                } else {
-                        goto cpu_reset;
-                }
-        }
 
-        /* Is this a secondary cpu? */
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        if (!boot_cpu()) {
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
-                if (last_boot_normal()) {
+                if (last_boot_normal_x) {
                         goto normal_image;
                 } else {
                         goto fallback_image;
@@ -186,7 +139,7 @@ void amd64_main(unsigned long bist)
         amd8111_enable_rom();
 
         /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal()) {
+        if (bios_reset_detected() && last_boot_normal_x) {
                 goto normal_image;
         }
         /* This is the primary cpu how should I boot? */
@@ -199,27 +152,29 @@ void amd64_main(unsigned long bist)
  normal_image:
         __asm__ volatile ("jmp __normal_image"
                 : /* outputs */
-                : "a" (bist) /* inputs */
+                : "a" (bist), "b" (cpu_init_detectedx)/* inputs */
                 );
- cpu_reset:
-#if 0
-        //CPU reset will reset memtroller ???
-        asm volatile ("jmp __cpu_reset" 
-                : /* outputs */ 
-                : "a"(bist) /* inputs */
-                );
-#endif
 
  fallback_image:
-        real_main(bist);
+	;
 }
-void real_main(unsigned long bist)
-#else
-void amd64_main(unsigned long bist)
 #endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+
+#if USE_FALLBACK_IMAGE == 1
+        failover_process(bist, cpu_init_detectedx);
+#endif
+        real_main(bist, cpu_init_detectedx);
+
+}
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
 		{
 			.node_id = 0,
 			.f0 = PCI_DEV(0, 0x18, 0),
@@ -229,8 +184,7 @@ void amd64_main(unsigned long bist)
 			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 		},
-#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
-#if SECOND_CPU
 		{
 			.node_id = 1,
 			.f0 = PCI_DEV(0, 0x19, 0),
@@ -247,57 +201,9 @@ void amd64_main(unsigned long bist)
 	unsigned cpu_reset = 0;
 
         if (bist == 0) {
-#if CONFIG_LOGICAL_CPUS==1
+		init_cpus(cpu_init_detectedx);
-        	struct node_core_id id;
-#else
-	        unsigned nodeid;
-#endif
-                /* Skip this if there was a built in self test failure */
-//                amd_early_mtrr_init(); # don't need, already done in cache_as_ram
-
-#if CONFIG_LOGICAL_CPUS==1
-                set_apicid_cpuid_lo();
-		id = get_node_core_id_x(); // that is initid
-#else
-                nodeid = get_node_id();
-#endif
-
-                enable_lapic();
-                init_timer();
-
-
-#if CONFIG_LOGICAL_CPUS==1
-                if(id.coreid == 0) {
-                        if (cpu_init_detected(id.nodeid)) {
-//                                __asm__ volatile ("jmp __cpu_reset");
-				cpu_reset = 1;
-				goto cpu_reset_x;
-                        }
-                        distinguish_cpu_resets(id.nodeid);
-//                        start_other_core(id.nodeid);
-                }
-#else
-                if (cpu_init_detected(nodeid)) {
-//                        __asm__ volatile ("jmp __cpu_reset");
-			cpu_reset = 1;
-			goto cpu_reset_x;
-                }
-                distinguish_cpu_resets(nodeid);
-#endif
-
-
-                if (!boot_cpu()
-#if CONFIG_LOGICAL_CPUS==1 
-                        || (id.coreid != 0)
-#endif
-                ) {
-			// We need stop the CACHE as RAM for this CPU too
-			#include "cpu/amd/car/cache_as_ram_post.c"
-                        stop_this_cpu(); // it will stop all cores except core0 of cpu0
-                }
         }
 
-	
  	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
         console_init();
@@ -310,6 +216,7 @@ void amd64_main(unsigned long bist)
 	needs_reset = setup_coherent_ht_domain();
 	
 #if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
         start_other_cores();
 #endif
         needs_reset |= ht_setup_chains_x();
@@ -324,90 +231,6 @@ void amd64_main(unsigned long bist)
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
-
+	post_cache_as_ram(cpu_reset);
-#if 1
-        {
-        /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
-        unsigned v_esp;
-        __asm__ volatile (
-                "movl   %%esp, %0\n\t"
-                : "=a" (v_esp)
-        );
-#if CONFIG_USE_INIT
-        printk_debug("v_esp=%08x\r\n", v_esp);
-#else           
-        print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
-#endif    
-        }
-#endif
-
-#if 1
-
-
-cpu_reset_x:
-
-#if CONFIG_USE_INIT
-        printk_debug("cpu_reset = %08x\r\n",cpu_reset);
-#else
-        print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
-#endif
-
-	if(cpu_reset == 0) {
-	        print_debug("Clearing initial memory region: ");
-	}
-	print_debug("No cache as ram now - ");
-
-	/* store cpu_reset to ebx */
-        __asm__ volatile (
-                "movl %0, %%ebx\n\t"
-                ::"a" (cpu_reset)
-        );
-
-	if(cpu_reset==0) {
-#define CLEAR_FIRST_1M_RAM 1
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-	else {
-#undef CLEAR_FIRST_1M_RAM 
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-
-	__asm__ volatile (
-                /* set new esp */ /* before _RAMBASE */
-                "subl   %0, %%ebp\n\t"
-                "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
-	);
-
-	{
-		unsigned new_cpu_reset;
-
-		/* get back cpu_reset from ebx */
-		__asm__ volatile (
-			"movl %%ebx, %0\n\t"
-			:"=a" (new_cpu_reset)
-		);
-
-		print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
-		if(new_cpu_reset==0) {        
-		        print_debug("done\r\n");	
-		} else 
-		{	
-			print_debug("\r\n");
-		}
-
-#if CONFIG_USE_INIT
-                printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
-#else
-                print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
-#endif
-		/*copy and execute linuxbios_ram */
-		copy_and_run(new_cpu_reset);
-		/* We will not return */
-	}
-#endif
-
-
-	print_debug("should not be here -\r\n");
 
 }

src/mainboard/tyan/s2880/Config.lb

@@ -93,9 +93,13 @@ end
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
+
 if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
@@ -204,11 +208,11 @@ chip northbridge/amd/amdk8/root_complex
                                                         device pci 9.0 on end #broadcom
 							device pci 9.1 on end 
                                                 end
-#                                                chip drivers/lsi/53c1030
+                                                chip drivers/lsi/53c1030
-#                                                        device pci a.0 on end
+                                                        device pci a.0 on end
-#                                                        device pci a.1 on end
+                                                        device pci a.1 on end
-#                                                        register "fw_address" = "0xfff8c000"
+                                                        register "fw_address" = "0xfff8c000"
-#                                                end
+                                                end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end

src/mainboard/tyan/s2880/Options.lb

@@ -52,7 +52,7 @@ uses OBJCOPY
 uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses K8_E0_MEM_HOLE_SIZEK
+uses K8_HW_MEM_HOLE_SIZEK
 
 uses USE_DCACHE_RAM
 uses DCACHE_RAM_BASE
@@ -71,7 +71,9 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=131072
+#256K
+default FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot
@@ -120,7 +122,7 @@ default CONFIG_LOGICAL_CPUS=0
 default CONFIG_CHIP_NAME=1
 
 #1G memory hole
-default K8_E0_MEM_HOLE_SIZEK=0x100000
+default K8_HW_MEM_HOLE_SIZEK=0x100000
 
 #VGA Console
 default CONFIG_CONSOLE_VGA=1

src/mainboard/tyan/s2880/cache_as_ram_auto.c

@@ -13,8 +13,8 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 
+
 #include "northbridge/amd/amdk8/cpu_rev.c"
-#define K8_HT_FREQ_1G_SUPPORT 0
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
@@ -36,27 +36,6 @@
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
 
 static void hard_reset(void)
 {
@@ -123,54 +102,28 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
-#include "cpu/amd/dualcore/dualcore.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
 #endif
-
+#include "cpu/amd/dualcore/dualcore.c"
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 
 #include "cpu/amd/car/copy_and_run.c"
 
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+
 #if USE_FALLBACK_IMAGE == 1
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-void real_main(unsigned long bist);
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-
-void amd64_main(unsigned long bist)
 {
-#if CONFIG_LOGICAL_CPUS==1
+        unsigned last_boot_normal_x = last_boot_normal();
-        struct node_core_id id;
-#else
-        unsigned nodeid;
-#endif
-        /* Make cerain my local apic is useable */
-//        enable_lapic();
 
-#if CONFIG_LOGICAL_CPUS==1
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        id = get_node_core_id_x();
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
-        /* Is this a cpu only reset? */
+                if (last_boot_normal_x) {
-        if (cpu_init_detected(id.nodeid)) {
-#else
-//        nodeid = lapicid();
-	nodeid = get_node_id();
-        /* Is this a cpu only reset? */
-        if (cpu_init_detected(nodeid)) {
-#endif
-                if (last_boot_normal()) {
-                        goto normal_image;
-                } else {
-                        goto cpu_reset;
-                }
-        }
-
-        /* Is this a secondary cpu? */
-        if (!boot_cpu()) {
-                if (last_boot_normal()) {
                         goto normal_image;
                 } else {
                         goto fallback_image;
@@ -182,11 +135,10 @@ void amd64_main(unsigned long bist)
 
         enumerate_ht_chain();
 
-        /* Setup the ck804 */
         amd8111_enable_rom();
 
         /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal()) {
+        if (bios_reset_detected() && last_boot_normal_x) {
                 goto normal_image;
         }
         /* This is the primary cpu how should I boot? */
@@ -199,27 +151,29 @@ void amd64_main(unsigned long bist)
  normal_image:
         __asm__ volatile ("jmp __normal_image"
                 : /* outputs */
-                : "a" (bist) /* inputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
                 );
- cpu_reset:
-#if 0
-        //CPU reset will reset memtroller ???
-        asm volatile ("jmp __cpu_reset" 
-                : /* outputs */ 
-                : "a"(bist) /* inputs */
-                );
-#endif
 
  fallback_image:
-        real_main(bist);
+	;
 }
-void real_main(unsigned long bist)
-#else
-void amd64_main(unsigned long bist)
 #endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+
+#if USE_FALLBACK_IMAGE == 1
+        failover_process(bist, cpu_init_detectedx);
+#endif
+        real_main(bist, cpu_init_detectedx);
+
+}
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
 		{
 			.node_id = 0,
 			.f0 = PCI_DEV(0, 0x18, 0),
@@ -229,8 +183,7 @@ void amd64_main(unsigned long bist)
 			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 		},
-#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
-#if SECOND_CPU
 		{
 			.node_id = 1,
 			.f0 = PCI_DEV(0, 0x19, 0),
@@ -247,51 +200,7 @@ void amd64_main(unsigned long bist)
 	unsigned cpu_reset = 0;
 
         if (bist == 0) {
-#if CONFIG_LOGICAL_CPUS==1
+		init_cpus(cpu_init_detectedx);
-        	struct node_core_id id;
-#else
-	        unsigned nodeid;
-#endif
-                /* Skip this if there was a built in self test failure */
-//                amd_early_mtrr_init(); # don't need, already done in cache_as_ram
-
-#if CONFIG_LOGICAL_CPUS==1
-                set_apicid_cpuid_lo();
-		id = get_node_core_id_x(); // that is initid
-#else
-                nodeid = get_node_id();
-#endif
-
-                enable_lapic();
-                init_timer();
-
-
-#if CONFIG_LOGICAL_CPUS==1
-                if(id.coreid == 0) {
-                        if (cpu_init_detected(id.nodeid)) {
-				cpu_reset = 1;
-				goto cpu_reset_x;
-                        }
-                        distinguish_cpu_resets(id.nodeid);
-                }
-#else
-                if (cpu_init_detected(nodeid)) {
-			cpu_reset = 1;
-			goto cpu_reset_x;
-                }
-                distinguish_cpu_resets(nodeid);
-#endif
-
-
-                if (!boot_cpu()
-#if CONFIG_LOGICAL_CPUS==1 
-                        || (id.coreid != 0)
-#endif
-                ) {
-			// We need stop the CACHE as RAM for this CPU too
-			#include "cpu/amd/car/cache_as_ram_post.c"
-                        stop_this_cpu(); // it will stop all cores except core0 of cpu0
-                }
         }
 
 	
@@ -307,8 +216,10 @@ void amd64_main(unsigned long bist)
 	needs_reset = setup_coherent_ht_domain();
 	
 #if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
         start_other_cores();
 #endif
+        // automatically set that for you, but you might meet tight space
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
@@ -321,89 +232,5 @@ void amd64_main(unsigned long bist)
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
-#if 1
+	post_cache_as_ram(cpu_reset);
-        {
-        /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
-        unsigned v_esp;
-        __asm__ volatile (
-                "movl   %%esp, %0\n\t"
-                : "=a" (v_esp)
-        );
-#if CONFIG_USE_INIT
-        printk_debug("v_esp=%08x\r\n", v_esp);
-#else           
-        print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
-#endif    
-        }
-#endif
-
-#if 1
-
-
-cpu_reset_x:
-
-#if CONFIG_USE_INIT
-        printk_debug("cpu_reset = %08x\r\n",cpu_reset);
-#else
-        print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
-#endif
-
-	if(cpu_reset == 0) {
-	        print_debug("Clearing initial memory region: ");
-	}
-	print_debug("No cache as ram now - ");
-
-	/* store cpu_reset to ebx */
-        __asm__ volatile (
-                "movl %0, %%ebx\n\t"
-                ::"a" (cpu_reset)
-        );
-
-	if(cpu_reset==0) {
-#define CLEAR_FIRST_1M_RAM 1
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-	else {
-#undef CLEAR_FIRST_1M_RAM 
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-
-	__asm__ volatile (
-                /* set new esp */ /* before _RAMBASE */
-                "subl   %0, %%ebp\n\t"
-                "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
-	);
-
-	{
-		unsigned new_cpu_reset;
-
-		/* get back cpu_reset from ebx */
-		__asm__ volatile (
-			"movl %%ebx, %0\n\t"
-			:"=a" (new_cpu_reset)
-		);
-
-		print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
-		if(new_cpu_reset==0) {        
-		        print_debug("done\r\n");	
-		} else 
-		{	
-			print_debug("\r\n");
-		}
-
-#if CONFIG_USE_INIT
-                printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
-#else
-                print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
-#endif
-		/*copy and execute linuxbios_ram */
-		copy_and_run(new_cpu_reset);
-		/* We will not return */
-	}
-#endif
-
-
-	print_debug("should not be here -\r\n");
-
 }

src/mainboard/tyan/s2881/Config.lb

@@ -93,9 +93,13 @@ end
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
+
 if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds

src/mainboard/tyan/s2881/Options.lb

@@ -52,7 +52,7 @@ uses OBJCOPY
 uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses K8_E0_MEM_HOLE_SIZEK
+uses K8_HW_MEM_HOLE_SIZEK
 
 uses USE_DCACHE_RAM
 uses DCACHE_RAM_BASE
@@ -71,7 +71,9 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=131072
+#256K
+default FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot
@@ -120,20 +122,20 @@ default CONFIG_LOGICAL_CPUS=1
 default CONFIG_CHIP_NAME=1
 
 #1G memory hole
-default K8_E0_MEM_HOLE_SIZEK=0x100000
+default K8_HW_MEM_HOLE_SIZEK=0x100000
 
 #VGA Console
-default CONFIG_CONSOLE_VGA=1
+#default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
+#default CONFIG_PCI_ROM_RUN=1
 
 
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=0
+default USE_DCACHE_RAM=1
 default DCACHE_RAM_BASE=0xcf000
 default DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
+default CONFIG_USE_INIT=1
 
 ##
 ## Build code to setup a generic IOAPIC

src/mainboard/tyan/s2881/cache_as_ram_auto.c

@@ -1,5 +1,11 @@
 #define ASSEMBLY 1
 #define __ROMCC__
+
+#define K8_4RANK_DIMM_SUPPORT 1
+
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
  
 #include <stdint.h>
 #include <device/pci_def.h>
@@ -13,9 +19,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 
-
 #include "northbridge/amd/amdk8/cpu_rev.c"
-#define K8_HT_FREQ_1G_SUPPORT 0
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
@@ -38,28 +42,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
-
 static void hard_reset(void)
 {
         device_t dev;
@@ -116,63 +98,34 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-#define K8_4RANK_DIMM_SUPPORT 1
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "resourcemap.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "sdram/generic_sdram.c"
 
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
 #include "cpu/amd/dualcore/dualcore.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
-#endif
 
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 
 #include "cpu/amd/car/copy_and_run.c"
 
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+
 #if USE_FALLBACK_IMAGE == 1
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-void real_main(unsigned long bist);
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-
-void amd64_main(unsigned long bist)
 {
-#if CONFIG_LOGICAL_CPUS==1
+        unsigned last_boot_normal_x = last_boot_normal();
-        struct node_core_id id;
-#else
-        unsigned nodeid;
-#endif
-        /* Make cerain my local apic is useable */
-//        enable_lapic();
 
-#if CONFIG_LOGICAL_CPUS==1
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        id = get_node_core_id_x();
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
-        /* Is this a cpu only reset? */
+                if (last_boot_normal_x) {
-        if (cpu_init_detected(id.nodeid)) {
-#else
-//        nodeid = lapicid();
-	nodeid = get_node_id();
-        /* Is this a cpu only reset? */
-        if (cpu_init_detected(nodeid)) {
-#endif
-                if (last_boot_normal()) {
-                        goto normal_image;
-                } else {
-                        goto cpu_reset;
-                }
-        }
-
-        /* Is this a secondary cpu? */
-        if (!boot_cpu()) {
-                if (last_boot_normal()) {
                         goto normal_image;
                 } else {
                         goto fallback_image;
@@ -184,11 +137,10 @@ void amd64_main(unsigned long bist)
 
         enumerate_ht_chain();
 
-        /* Setup the ck804 */
         amd8111_enable_rom();
 
         /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal()) {
+        if (bios_reset_detected() && last_boot_normal_x) {
                 goto normal_image;
         }
         /* This is the primary cpu how should I boot? */
@@ -201,99 +153,46 @@ void amd64_main(unsigned long bist)
  normal_image:
         __asm__ volatile ("jmp __normal_image"
                 : /* outputs */
-                : "a" (bist) /* inputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
                 );
- cpu_reset:
-#if 0
-        //CPU reset will reset memtroller ???
-        asm volatile ("jmp __cpu_reset" 
-                : /* outputs */ 
-                : "a"(bist) /* inputs */
-                );
-#endif
 
  fallback_image:
-        real_main(bist);
+	;
 }
-void real_main(unsigned long bist)
-#else
-void amd64_main(unsigned long bist)
 #endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	static const struct mem_controller cpu[] = {
+
-#if FIRST_CPU
+#if USE_FALLBACK_IMAGE == 1
-		{
+        failover_process(bist, cpu_init_detectedx);
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
 #endif
-#if SECOND_CPU
+        real_main(bist, cpu_init_detectedx);
-		{
+
-			.node_id = 1,
+}
-			.f0 = PCI_DEV(0, 0x19, 0),
+
-			.f1 = PCI_DEV(0, 0x19, 1),
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-			.f2 = PCI_DEV(0, 0x19, 2),
+{
-			.f3 = PCI_DEV(0, 0x19, 3),
+	static const uint16_t spd_addr [] = {
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
+			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
+			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
-		},
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
+			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
 #endif
 	};
 
         int needs_reset;
 	unsigned cpu_reset = 0;
+        unsigned bsp_apicid = 0;
+
+        struct mem_controller ctrl[8];
+        unsigned nodes;
 
         if (bist == 0) {
-#if CONFIG_LOGICAL_CPUS==1
+                bsp_apicid = init_cpus(cpu_init_detectedx);
-        	struct node_core_id id;
-#else
-	        unsigned nodeid;
-#endif
-                /* Skip this if there was a built in self test failure */
-//                amd_early_mtrr_init(); # don't need, already done in cache_as_ram
-
-#if CONFIG_LOGICAL_CPUS==1
-                set_apicid_cpuid_lo();
-		id = get_node_core_id_x(); // that is initid
-#else
-                nodeid = get_node_id();
-#endif
-
-                enable_lapic();
-                init_timer();
-
-
-#if CONFIG_LOGICAL_CPUS==1
-                if(id.coreid == 0) {
-                        if (cpu_init_detected(id.nodeid)) {
-				cpu_reset = 1;
-				goto cpu_reset_x;
-                        }
-                        distinguish_cpu_resets(id.nodeid);
-                }
-#else
-                if (cpu_init_detected(nodeid)) {
-			cpu_reset = 1;
-			goto cpu_reset_x;
-                }
-                distinguish_cpu_resets(nodeid);
-#endif
-
-
-                if (!boot_cpu()
-#if CONFIG_LOGICAL_CPUS==1 
-                        || (id.coreid != 0)
-#endif
-                ) {
-			// We need stop the CACHE as RAM for this CPU too
-			#include "cpu/amd/car/cache_as_ram_post.c"
-                        stop_this_cpu(); // it will stop all cores except core0 of cpu0
-                }
         }
 
 	
@@ -310,8 +209,12 @@ void amd64_main(unsigned long bist)
 	
 #if CONFIG_LOGICAL_CPUS==1
         // It is said that we should start core1 after all core0 launched
+	wait_all_core0_started();
         start_other_cores();
 #endif
+
+        wait_all_aps_started(bsp_apicid);
+
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
@@ -321,92 +224,15 @@ void amd64_main(unsigned long bist)
 
 	enable_smbus();
 
-	memreset_setup();
+        allow_all_aps_stop(bsp_apicid);
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
-#if 1
+        nodes = get_nodes();
-        {
+        //It's the time to set ctrl now;
-        /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
+        fill_mem_ctrl(nodes, ctrl, spd_addr);
-        unsigned v_esp;
-        __asm__ volatile (
-                "movl   %%esp, %0\n\t"
-                : "=a" (v_esp)
-        );
-#if CONFIG_USE_INIT
-        printk_debug("v_esp=%08x\r\n", v_esp);
-#else           
-        print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
-#endif    
-        }
-#endif
 
-#if 1
+        memreset_setup();
+        sdram_initialize(nodes, ctrl);
 
 
-cpu_reset_x:
+	post_cache_as_ram(cpu_reset);
-
-#if CONFIG_USE_INIT
-        printk_debug("cpu_reset = %08x\r\n",cpu_reset);
-#else
-        print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
-#endif
-
-	if(cpu_reset == 0) {
-	        print_debug("Clearing initial memory region: ");
-	}
-	print_debug("No cache as ram now - ");
-
-	/* store cpu_reset to ebx */
-        __asm__ volatile (
-                "movl %0, %%ebx\n\t"
-                ::"a" (cpu_reset)
-        );
-
-	if(cpu_reset==0) {
-#define CLEAR_FIRST_1M_RAM 1
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-	else {
-#undef CLEAR_FIRST_1M_RAM 
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-
-	__asm__ volatile (
-                /* set new esp */ /* before _RAMBASE */
-                "subl   %0, %%ebp\n\t"
-                "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
-	);
-
-	{
-		unsigned new_cpu_reset;
-
-		/* get back cpu_reset from ebx */
-		__asm__ volatile (
-			"movl %%ebx, %0\n\t"
-			:"=a" (new_cpu_reset)
-		);
-
-		print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
-		if(new_cpu_reset==0) {        
-		        print_debug("done\r\n");	
-		} else 
-		{	
-			print_debug("\r\n");
-		}
-
-#if CONFIG_USE_INIT
-                printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
-#else
-                print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
-#endif
-		/*copy and execute linuxbios_ram */
-		copy_and_run(new_cpu_reset);
-		/* We will not return */
-	}
-#endif
-
-
-	print_debug("should not be here -\r\n");
-
 }

src/mainboard/tyan/s2882/Config.lb

@@ -93,9 +93,13 @@ end
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
+
 if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds

src/mainboard/tyan/s2882/Options.lb

@@ -52,7 +52,7 @@ uses OBJCOPY
 uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses K8_E0_MEM_HOLE_SIZEK
+uses K8_HW_MEM_HOLE_SIZEK
 
 uses USE_DCACHE_RAM
 uses DCACHE_RAM_BASE
@@ -71,7 +71,9 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=131072
+#256K
+default FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot
@@ -120,7 +122,7 @@ default CONFIG_LOGICAL_CPUS=1
 default CONFIG_CHIP_NAME=1
 
 #1G memory hole
-default K8_E0_MEM_HOLE_SIZEK=0x100000
+default K8_HW_MEM_HOLE_SIZEK=0x100000
 
 #VGA Console
 default CONFIG_CONSOLE_VGA=1
@@ -130,10 +132,10 @@ default CONFIG_PCI_ROM_RUN=1
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=0
+default USE_DCACHE_RAM=1
 default DCACHE_RAM_BASE=0xcf000
 default DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
+default CONFIG_USE_INIT=1
 
 ##
 ## Build code to setup a generic IOAPIC

src/mainboard/tyan/s2882/cache_as_ram_auto.c

@@ -14,7 +14,6 @@
 #include "ram/ramtest.c"
 
 #include "northbridge/amd/amdk8/cpu_rev.c"
-#define K8_HT_FREQ_1G_SUPPORT 0
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
@@ -36,27 +35,6 @@
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
 
 static void hard_reset(void)
 {
@@ -123,10 +101,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
-#include "cpu/amd/dualcore/dualcore.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
 #endif
+#include "cpu/amd/dualcore/dualcore.c"
 
 #define FIRST_CPU  1
 #define SECOND_CPU 1
@@ -134,43 +110,23 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/car/copy_and_run.c"
 
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+
 #if USE_FALLBACK_IMAGE == 1
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-void real_main(unsigned long bist);
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-
-void amd64_main(unsigned long bist)
 {
-#if CONFIG_LOGICAL_CPUS==1
+        unsigned last_boot_normal_x = last_boot_normal();
-        struct node_core_id id;
-#else
-        unsigned nodeid;
-#endif
-        /* Make cerain my local apic is useable */
-//        enable_lapic();
 
-#if CONFIG_LOGICAL_CPUS==1
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        id = get_node_core_id_x();
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
-        /* Is this a cpu only reset? */
+                if (last_boot_normal_x) {
-        if (cpu_init_detected(id.nodeid)) {
-#else
-//        nodeid = lapicid();
-	nodeid = get_node_id();
-        /* Is this a cpu only reset? */
-        if (cpu_init_detected(nodeid)) {
-#endif
-                if (last_boot_normal()) {
-                        goto normal_image;
-                } else {
-                        goto cpu_reset;
-                }
-        }
-
-        /* Is this a secondary cpu? */
-        if (!boot_cpu()) {
-                if (last_boot_normal()) {
                         goto normal_image;
                 } else {
                         goto fallback_image;
@@ -182,11 +138,10 @@ void amd64_main(unsigned long bist)
 
         enumerate_ht_chain();
 
-        /* Setup the ck804 */
         amd8111_enable_rom();
 
         /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal()) {
+        if (bios_reset_detected() && last_boot_normal_x) {
                 goto normal_image;
         }
         /* This is the primary cpu how should I boot? */
@@ -199,27 +154,29 @@ void amd64_main(unsigned long bist)
  normal_image:
         __asm__ volatile ("jmp __normal_image"
                 : /* outputs */
-                : "a" (bist) /* inputs */
+                : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */
                 );
- cpu_reset:
-#if 0
-        //CPU reset will reset memtroller ???
-        asm volatile ("jmp __cpu_reset" 
-                : /* outputs */ 
-                : "a"(bist) /* inputs */
-                );
-#endif
 
  fallback_image:
-        real_main(bist);
+	;
 }
-void real_main(unsigned long bist)
-#else
-void amd64_main(unsigned long bist)
 #endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+
+#if USE_FALLBACK_IMAGE == 1
+        failover_process(bist, cpu_init_detectedx);
+#endif
+        real_main(bist, cpu_init_detectedx);
+
+}
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
 		{
 			.node_id = 0,
 			.f0 = PCI_DEV(0, 0x18, 0),
@@ -229,8 +186,7 @@ void amd64_main(unsigned long bist)
 			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 		},
-#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
-#if SECOND_CPU
 		{
 			.node_id = 1,
 			.f0 = PCI_DEV(0, 0x19, 0),
@@ -247,53 +203,10 @@ void amd64_main(unsigned long bist)
 	unsigned cpu_reset = 0;
 
         if (bist == 0) {
-#if CONFIG_LOGICAL_CPUS==1
+		init_cpus(cpu_init_detectedx);
-        	struct node_core_id id;
-#else
-	        unsigned nodeid;
-#endif
-                /* Skip this if there was a built in self test failure */
-//                amd_early_mtrr_init(); # don't need, already done in cache_as_ram
-
-#if CONFIG_LOGICAL_CPUS==1
-                set_apicid_cpuid_lo();
-		id = get_node_core_id_x(); // that is initid
-#else
-                nodeid = get_node_id();
-#endif
-
-                enable_lapic();
-                init_timer();
-
-
-#if CONFIG_LOGICAL_CPUS==1
-                if(id.coreid == 0) {
-                        if (cpu_init_detected(id.nodeid)) {
-//                                __asm__ volatile ("jmp __cpu_reset");
-				cpu_reset = 1;
-				goto cpu_reset_x;
-                        }
-                        distinguish_cpu_resets(id.nodeid);
-                }
-#else
-                if (cpu_init_detected(nodeid)) {
-			cpu_reset = 1;
-			goto cpu_reset_x;
-                }
-                distinguish_cpu_resets(nodeid);
-#endif
-
-                if (!boot_cpu()
-#if CONFIG_LOGICAL_CPUS==1 
-                        || (id.coreid != 0)
-#endif
-                ) {
-			// We need stop the CACHE as RAM for this CPU too
-			#include "cpu/amd/car/cache_as_ram_post.c"
-                        stop_this_cpu(); // it will stop all cores except core0 of cpu0
-                }
         }
 
+	
  	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
         console_init();
@@ -309,6 +222,7 @@ void amd64_main(unsigned long bist)
         // It is said that we should start core1 after all core0 launched
         start_other_cores();
 #endif
+        // automatically set that for you, but you might meet tight space
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
@@ -321,89 +235,6 @@ void amd64_main(unsigned long bist)
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
-#if 1
+	post_cache_as_ram(cpu_reset);
-        {
-        /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
-        unsigned v_esp;
-        __asm__ volatile (
-                "movl   %%esp, %0\n\t"
-                : "=a" (v_esp)
-        );
-#if CONFIG_USE_INIT
-        printk_debug("v_esp=%08x\r\n", v_esp);
-#else           
-        print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
-#endif    
-        }
-#endif
-
-#if 1
-
-
-cpu_reset_x:
-
-#if CONFIG_USE_INIT
-        printk_debug("cpu_reset = %08x\r\n",cpu_reset);
-#else
-        print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
-#endif
-
-	if(cpu_reset == 0) {
-	        print_debug("Clearing initial memory region: ");
-	}
-	print_debug("No cache as ram now - ");
-
-	/* store cpu_reset to ebx */
-        __asm__ volatile (
-                "movl %0, %%ebx\n\t"
-                ::"a" (cpu_reset)
-        );
-
-	if(cpu_reset==0) {
-#define CLEAR_FIRST_1M_RAM 1
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-	else {
-#undef CLEAR_FIRST_1M_RAM 
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-
-	__asm__ volatile (
-                /* set new esp */ /* before _RAMBASE */
-                "subl   %0, %%ebp\n\t"
-                "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
-	);
-
-	{
-		unsigned new_cpu_reset;
-
-		/* get back cpu_reset from ebx */
-		__asm__ volatile (
-			"movl %%ebx, %0\n\t"
-			:"=a" (new_cpu_reset)
-		);
-
-		print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
-		if(new_cpu_reset==0) {        
-		        print_debug("done\r\n");	
-		} else 
-		{	
-			print_debug("\r\n");
-		}
-
-#if CONFIG_USE_INIT
-                printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
-#else
-                print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
-#endif
-		/*copy and execute linuxbios_ram */
-		copy_and_run(new_cpu_reset);
-		/* We will not return */
-	}
-#endif
-
-
-	print_debug("should not be here -\r\n");
 
 }

src/mainboard/tyan/s2885/Config.lb

@@ -93,9 +93,13 @@ end
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
+
 if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds

src/mainboard/tyan/s2885/Options.lb

@@ -52,13 +52,17 @@ uses OBJCOPY
 uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses K8_E0_MEM_HOLE_SIZEK
+uses K8_HW_MEM_HOLE_SIZEK
 
 uses USE_DCACHE_RAM
 uses DCACHE_RAM_BASE
 uses DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 
+uses ENABLE_APIC_EXT_ID
+uses APIC_ID_OFFSET
+uses LIFT_BSP_APIC_ID
+
 ###
 ### Build options
 ###
@@ -71,7 +75,9 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=131072
+#256K
+default FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot
@@ -120,7 +126,7 @@ default CONFIG_LOGICAL_CPUS=1
 default CONFIG_CHIP_NAME=1
 
 #1G memory hole
-default K8_E0_MEM_HOLE_SIZEK=0x100000
+default K8_HW_MEM_HOLE_SIZEK=0x100000
 
 #VGA Console
 default CONFIG_CONSOLE_VGA=1
@@ -130,10 +136,14 @@ default CONFIG_PCI_ROM_RUN=1
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=0
+default USE_DCACHE_RAM=1
 default DCACHE_RAM_BASE=0xcf000
 default DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
+default CONFIG_USE_INIT=1
+
+default ENABLE_APIC_EXT_ID=1
+default APIC_ID_OFFSET=0x10
+default LIFT_BSP_APIC_ID=0
 
 ##
 ## Build code to setup a generic IOAPIC

src/mainboard/tyan/s2885/cache_as_ram_auto.c

@@ -14,7 +14,6 @@
 #include "ram/ramtest.c"
 
 #include "northbridge/amd/amdk8/cpu_rev.c"
-#define K8_HT_FREQ_1G_SUPPORT 0
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
@@ -37,28 +36,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
-
 static void hard_reset(void)
 {
         device_t dev;
@@ -118,13 +95,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define K8_4RANK_DIMM_SUPPORT 1
 
 #include "northbridge/amd/amdk8/raminit.c"
-#if 0
-        #define ENABLE_APIC_EXT_ID 1
-        #define APIC_ID_OFFSET 0x10
-        #define LIFT_BSP_APIC_ID 0
-#else 
-        #define ENABLE_APIC_EXT_ID 0
-#endif
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "sdram/generic_sdram.c"
 
@@ -133,54 +103,29 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
-#include "cpu/amd/dualcore/dualcore.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
 #endif
+#include "cpu/amd/dualcore/dualcore.c"
 
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 
 #include "cpu/amd/car/copy_and_run.c"
 
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+
 #if USE_FALLBACK_IMAGE == 1
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-void real_main(unsigned long bist);
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-
-void amd64_main(unsigned long bist)
 {
-#if CONFIG_LOGICAL_CPUS==1
+        unsigned last_boot_normal_x = last_boot_normal();
-        struct node_core_id id;
-#else
-        unsigned nodeid;
-#endif
-        /* Make cerain my local apic is useable */
-//        enable_lapic();
 
-#if CONFIG_LOGICAL_CPUS==1
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        id = get_node_core_id_x();
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
-        /* Is this a cpu only reset? */
+                if (last_boot_normal_x) {
-        if (cpu_init_detected(id.nodeid)) {
-#else
-//        nodeid = lapicid();
-	nodeid = get_node_id();
-        /* Is this a cpu only reset? */
-        if (cpu_init_detected(nodeid)) {
-#endif
-                if (last_boot_normal()) {
-                        goto normal_image;
-                } else {
-                        goto cpu_reset;
-                }
-        }
-
-        /* Is this a secondary cpu? */
-        if (!boot_cpu()) {
-                if (last_boot_normal()) {
                         goto normal_image;
                 } else {
                         goto fallback_image;
@@ -192,11 +137,10 @@ void amd64_main(unsigned long bist)
 
         enumerate_ht_chain();
 
-        /* Setup the ck804 */
         amd8111_enable_rom();
 
         /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal()) {
+        if (bios_reset_detected() && last_boot_normal_x) {
                 goto normal_image;
         }
         /* This is the primary cpu how should I boot? */
@@ -209,120 +153,46 @@ void amd64_main(unsigned long bist)
  normal_image:
         __asm__ volatile ("jmp __normal_image"
                 : /* outputs */
-                : "a" (bist) /* inputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
                 );
- cpu_reset:
-#if 0
-        //CPU reset will reset memtroller ???
-        asm volatile ("jmp __cpu_reset" 
-                : /* outputs */ 
-                : "a"(bist) /* inputs */
-                );
-#endif
 
  fallback_image:
-        real_main(bist);
+	;
 }
-void real_main(unsigned long bist)
-#else
-void amd64_main(unsigned long bist)
 #endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	static const struct mem_controller cpu[] = {
+
-#if FIRST_CPU
+#if USE_FALLBACK_IMAGE == 1
-		{
+        failover_process(bist, cpu_init_detectedx);
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
 #endif
-#if SECOND_CPU
+        real_main(bist, cpu_init_detectedx);
-		{
+
-			.node_id = 1,
+}
-			.f0 = PCI_DEV(0, 0x19, 0),
+
-			.f1 = PCI_DEV(0, 0x19, 1),
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-			.f2 = PCI_DEV(0, 0x19, 2),
+{
-			.f3 = PCI_DEV(0, 0x19, 3),
+	static const uint16_t spd_addr [] = {
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
+			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
+			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
-		},
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
+			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
 #endif
 	};
 
         int needs_reset;
 	unsigned cpu_reset = 0;
+        unsigned bsp_apicid = 0;
+
+        struct mem_controller ctrl[8];
+        unsigned nodes;
 
         if (bist == 0) {
-#if CONFIG_LOGICAL_CPUS==1
+                bsp_apicid = init_cpus(cpu_init_detectedx);
-        	struct node_core_id id;
-#else
-	        unsigned nodeid;
-#endif
-                /* Skip this if there was a built in self test failure */
-//                amd_early_mtrr_init(); # don't need, already done in cache_as_ram
-
-#if CONFIG_LOGICAL_CPUS==1
-                set_apicid_cpuid_lo();
-		id = get_node_core_id_x(); // that is initid
-        #if ENABLE_APIC_EXT_ID == 1
-                if(id.coreid == 0) {
-                        enable_apic_ext_id(id.nodeid);
-                }
-        #endif
-#else
-                nodeid = get_node_id();
-        #if ENABLE_APIC_EXT_ID == 1
-                enable_apic_ext_id(nodeid);
-        #endif
-#endif
-
-                enable_lapic();
-                init_timer();
-
-
-#if CONFIG_LOGICAL_CPUS==1
-        #if ENABLE_APIC_EXT_ID == 1
-            #if LIFT_BSP_APIC_ID == 0
-                if( id.nodeid != 0 ) //all except cores in node0
-            #endif
-                        lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) );
-        #endif
-                if(id.coreid == 0) {
-                        if (cpu_init_detected(id.nodeid)) {
-				cpu_reset = 1;
-				goto cpu_reset_x;
-                        }
-                        distinguish_cpu_resets(id.nodeid);
-                }
-#else
-        #if ENABLE_APIC_EXT_ID == 1
-            #if LIFT_BSP_APIC_ID == 0
-                if(nodeid != 0)
-            #endif
-                        lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10
-
-        #endif
-                if (cpu_init_detected(nodeid)) {
-			cpu_reset = 1;
-			goto cpu_reset_x;
-                }
-                distinguish_cpu_resets(nodeid);
-#endif
-
-
-                if (!boot_cpu()
-#if CONFIG_LOGICAL_CPUS==1 
-                        || (id.coreid != 0)
-#endif
-                ) {
-			// We need stop the CACHE as RAM for this CPU too
-			#include "cpu/amd/car/cache_as_ram_post.c"
-                        stop_this_cpu(); // it will stop all cores except core0 of cpu0
-                }
         }
 
 	
@@ -338,8 +208,13 @@ void amd64_main(unsigned long bist)
 	needs_reset = setup_coherent_ht_domain();
 	
 #if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
+	wait_all_core0_started();
         start_other_cores();
 #endif
+
+        wait_all_aps_started(bsp_apicid);
+
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
@@ -347,94 +222,18 @@ void amd64_main(unsigned long bist)
                	soft_reset();
        	}
 
-	enable_smbus();
 
-	memreset_setup();
+        allow_all_aps_stop(bsp_apicid);
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
-#if 1
+        nodes = get_nodes();
-        {
+        //It's the time to set ctrl now;
-        /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
+        fill_mem_ctrl(nodes, ctrl, spd_addr);
-        unsigned v_esp;
-        __asm__ volatile (
-                "movl   %%esp, %0\n\t"
-                : "=a" (v_esp)
-        );
-#if CONFIG_USE_INIT
-        printk_debug("v_esp=%08x\r\n", v_esp);
-#else           
-        print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
-#endif    
-        }
-#endif
 
-#if 1
+        enable_smbus();
 
+        memreset_setup();
+        sdram_initialize(nodes, ctrl);
 
-cpu_reset_x:
+	post_cache_as_ram(cpu_reset);
-
-#if CONFIG_USE_INIT
-        printk_debug("cpu_reset = %08x\r\n",cpu_reset);
-#else
-        print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
-#endif
-
-	if(cpu_reset == 0) {
-	        print_debug("Clearing initial memory region: ");
-	}
-	print_debug("No cache as ram now - ");
-
-	/* store cpu_reset to ebx */
-        __asm__ volatile (
-                "movl %0, %%ebx\n\t"
-                ::"a" (cpu_reset)
-        );
-
-	if(cpu_reset==0) {
-#define CLEAR_FIRST_1M_RAM 1
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-	else {
-#undef CLEAR_FIRST_1M_RAM 
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-
-	__asm__ volatile (
-                /* set new esp */ /* before _RAMBASE */
-                "subl   %0, %%ebp\n\t"
-                "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
-	);
-
-	{
-		unsigned new_cpu_reset;
-
-		/* get back cpu_reset from ebx */
-		__asm__ volatile (
-			"movl %%ebx, %0\n\t"
-			:"=a" (new_cpu_reset)
-		);
-
-		print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
-		if(new_cpu_reset==0) {        
-		        print_debug("done\r\n");	
-		} else 
-		{	
-			print_debug("\r\n");
-		}
-
-#if CONFIG_USE_INIT
-                printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
-#else
-                print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
-#endif
-		/*copy and execute linuxbios_ram */
-		copy_and_run(new_cpu_reset);
-		/* We will not return */
-	}
-#endif
-
-
-	print_debug("should not be here -\r\n");
 
 }

src/mainboard/tyan/s2891/Config.lb

@@ -97,9 +97,13 @@ end
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
+
 
 if USE_DCACHE_RAM
 	if CONFIG_USE_INIT
@@ -213,7 +217,7 @@ chip northbridge/amd/amdk8/root_complex
 					device pci 0.0 on end   # HT
                 			device pci 1.0 on # LPC
                                         	chip superio/winbond/w83627hf
-                                                	device pnp 2e.0 on #  Floppy
+                                                	device pnp 2e.0 off #  Floppy
                                                         	io 0x60 = 0x3f0
 	                                                        irq 0x70 = 6
         	                                                drq 0x74 = 2
@@ -226,11 +230,11 @@ chip northbridge/amd/amdk8/root_complex
         	                                                io 0x60 = 0x3f8
                 	                                        irq 0x70 = 4
                         	                        end
-                                	                device pnp 2e.3 on #  Com2
+                                	                device pnp 2e.3 off #  Com2
                                         	                io 0x60 = 0x2f8
                                                 	        irq 0x70 = 3
 	                                                end
-        	                                        device pnp 2e.5 on #  Keyboard
+        	                                        device pnp 2e.5 off #  Keyboard
                 	                                        io 0x60 = 0x60
                         	                                io 0x62 = 0x64
                                 	                        irq 0x70 = 1
@@ -247,55 +251,55 @@ chip northbridge/amd/amdk8/root_complex
         	                                        device pnp 2e.8 off end #  GPIO2
                 	                                device pnp 2e.9 off end #  GPIO3
                         	                        device pnp 2e.a off end #  ACPI
-                                	                device pnp 2e.b on #  HW Monitor
+                                	                device pnp 2e.b off #  HW Monitor
                                         	                io 0x60 = 0x290
                                                 	        irq 0x70 = 5
 	                                                end
         	                                end
 					end
                                         device pci 1.1 on # SM 0
-                                                chip drivers/generic/generic #dimm 0-0-0
+#                                                chip drivers/generic/generic #dimm 0-0-0
-                                                        device i2c 50 on end
+#                                                        device i2c 50 on end
-                                                end
+#                                                end
-                                                chip drivers/generic/generic #dimm 0-0-1
+#                                                chip drivers/generic/generic #dimm 0-0-1
-                                                        device i2c 51 on end
+#                                                        device i2c 51 on end
-                                                end
+#                                                end
-                                                chip drivers/generic/generic #dimm 0-1-0
+#                                                chip drivers/generic/generic #dimm 0-1-0
-                                                        device i2c 52 on end
+#                                                        device i2c 52 on end
-                                                end
+#                                                end
-                                                chip drivers/generic/generic #dimm 0-1-1
+#                                                chip drivers/generic/generic #dimm 0-1-1
-                                                        device i2c 53 on end
+#                                                        device i2c 53 on end
-                                                end
+#                                                end
-                                                chip drivers/generic/generic #dimm 1-0-0
+#                                                chip drivers/generic/generic #dimm 1-0-0
-                                                        device i2c 54 on end
+#                                                        device i2c 54 on end
-                                                end
+#                                                end
-                                                chip drivers/generic/generic #dimm 1-0-1
+#                                                chip drivers/generic/generic #dimm 1-0-1
-                                                        device i2c 55 on end
+#                                                        device i2c 55 on end
-                                                end
+#                                                end
-                                                chip drivers/generic/generic #dimm 1-1-0
+#                                                chip drivers/generic/generic #dimm 1-1-0
-                                                        device i2c 56 on end
+#                                                        device i2c 56 on end
-                                                end
+#                                                end
-                                                chip drivers/generic/generic #dimm 1-1-1
+#                                                chip drivers/generic/generic #dimm 1-1-1
-                                                        device i2c 57 on end
+#                                                        device i2c 57 on end
-                                                end
+#                                                end
                                         end # SM
-		        	        device pci 1.1 on # SM 1
+#		        	        device pci 1.1 on # SM 1
-						chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
+#						chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
-                                                	device i2c 2d on end
+#                                                	device i2c 2d on end
-                                                end
+#                                                end
-                                                chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 
+#                                                chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 
-		                                        device i2c 2e on end
+#		                                        device i2c 2e on end
-                                                end
+#                                                end
-                                                chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
+#                                                chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
-                                                        device i2c 2a on end
+#                                                        device i2c 2a on end
-                                                end
+#                                                end
-                                                chip drivers/generic/generic # Winbond HWM 0x92
+#                                                chip drivers/generic/generic # Winbond HWM 0x92
-                                                        device i2c 49 on end
+#                                                        device i2c 49 on end
-                                                end
+#                                                end
-                                                chip drivers/generic/generic # Winbond HWM 0x94
+#                                                chip drivers/generic/generic # Winbond HWM 0x94
-                                                        device i2c 4a on end
+#                                                        device i2c 4a on end
-                                                end
+#                                                end
-					end #SM
+#					end #SM
                 			device pci 2.0 on end # USB 1.1
 	                		device pci 2.1 on end # USB 2
         	        		device pci 4.0 off end # ACI
@@ -307,8 +311,8 @@ chip northbridge/amd/amdk8/root_complex
 					#	chip drivers/ati/ragexl
                                                 chip drivers/pci/onboard
                                                         device pci 7.0 on end
-                                                        register "rom_address" = "0xfff80000" #for 512K
+                                        #                register "rom_address" = "0xfff80000" #for 512K
-							#register "rom_address" = "0xfff00000" #for 1M
+							register "rom_address" = "0xfff00000" #for 1M
                                                 end
 					end
                 			device pci a.0 off end # NIC

src/mainboard/tyan/s2891/Options.lb

@@ -53,7 +53,7 @@ uses CONFIG_GDB_STUB
 uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses K8_E0_MEM_HOLE_SIZEK
+uses K8_HW_MEM_HOLE_SIZEK
 
 uses CK804_DEVN_BASE
 
@@ -62,18 +62,26 @@ uses DCACHE_RAM_BASE
 uses DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 
+uses ENABLE_APIC_EXT_ID
+uses APIC_ID_OFFSET
+uses LIFT_BSP_APIC_ID
+
+uses CONFIG_PCI_64BIT_PREF_MEM
+
 ## ROM_SIZE is the size of boot ROM that this board will use.
 #512K bytes 
-default ROM_SIZE=524288
+#default ROM_SIZE=524288
 
 #1M bytes
-#default ROM_SIZE=1048576
+default ROM_SIZE=1048576
 
 
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=131072
+#256K
+default FALLBACK_SIZE=0x40000
 
 ###
 ### Build options
@@ -123,27 +131,33 @@ default CONFIG_MAX_PHYSICAL_CPUS=2
 default CONFIG_LOGICAL_CPUS=1
 
 #1G memory hole
-default K8_E0_MEM_HOLE_SIZEK=0x100000
+default K8_HW_MEM_HOLE_SIZEK=0x100000
 
 #CK804 setting
 
-#default CK804_DEVN_BASE=0
+default CK804_DEVN_BASE=0
 
 #BTEXT Console
 #default CONFIG_CONSOLE_BTEXT=1
 
 #VGA Console
-#default CONFIG_CONSOLE_VGA=1
+default CONFIG_CONSOLE_VGA=1
-#default CONFIG_PCI_ROM_RUN=1
+default CONFIG_PCI_ROM_RUN=1
 
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=0
+default USE_DCACHE_RAM=1
 default DCACHE_RAM_BASE=0xcf000
 default DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
+default CONFIG_USE_INIT=1
 
+default ENABLE_APIC_EXT_ID=1
+default APIC_ID_OFFSET=0x10
+default LIFT_BSP_APIC_ID=0
+
+
+#default CONFIG_PCI_64BIT_PREF_MEM=1
 
 ##
 ## Build code to setup a generic IOAPIC

src/mainboard/tyan/s2891/cache_as_ram_auto.c

@@ -1,5 +1,13 @@
 #define ASSEMBLY 1
 #define __ROMCC__
+
+//used by raminit
+#define K8_4RANK_DIMM_SUPPORT 1
+
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
+
  
 #include <stdint.h>
 #include <device/pci_def.h>
@@ -14,8 +22,6 @@
 #include "ram/ramtest.c"
 
 #include "northbridge/amd/amdk8/cpu_rev.c"
-//#define K8_HT_FREQ_1G_SUPPORT 1
-//#define K8_SCAN_PCI_BUS 1
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
@@ -73,8 +79,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-#define K8_4RANK_DIMM_SUPPORT 1
-
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "sdram/generic_sdram.c"
@@ -82,16 +86,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
  /* tyan does not want the default */
 #include "resourcemap.c" 
 
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
 #include "cpu/amd/dualcore/dualcore.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
-#endif
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 
 #define CK804_NUM 1
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
@@ -99,6 +94,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/car/copy_and_run.c"
 
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+
 #if USE_FALLBACK_IMAGE == 1
 
 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
@@ -127,38 +127,14 @@ static void sio_setup(void)
 #endif
 
 }
-void real_main(unsigned long bist);
 
-void amd64_main(unsigned long bist)
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if CONFIG_LOGICAL_CPUS==1
+        unsigned last_boot_normal_x = last_boot_normal();
-        struct node_core_id id;
-#else
-        unsigned nodeid;
-#endif
-        /* Make cerain my local apic is useable */
-//        enable_lapic();
 
-#if CONFIG_LOGICAL_CPUS==1
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        id = get_node_core_id_x();
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
-        /* Is this a cpu only reset? */
+                if (last_boot_normal_x) {
-        if (cpu_init_detected(id.nodeid)) {
-#else
-//        nodeid = lapicid() & 0xf;
-        nodeid = get_node_id();
-        /* Is this a cpu only reset? */
-        if (cpu_init_detected(nodeid)) {
-#endif
-                if (last_boot_normal()) {
-                        goto normal_image;
-                } else {
-                        goto cpu_reset;
-                }
-        }
-
-        /* Is this a secondary cpu? */
-        if (!boot_cpu()) {
-                if (last_boot_normal()) {
                         goto normal_image;
                 } else {
                         goto fallback_image;
@@ -176,7 +152,7 @@ void amd64_main(unsigned long bist)
         ck804_enable_rom();
 
         /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal()) {
+        if (bios_reset_detected() && last_boot_normal_x) {
                 goto normal_image;
         }
         /* This is the primary cpu how should I boot? */
@@ -189,105 +165,48 @@ void amd64_main(unsigned long bist)
  normal_image:
         __asm__ volatile ("jmp __normal_image"
                 : /* outputs */
-                : "a" (bist) /* inputs */
+                : "a" (bist) , "b" (cpu_init_detectedx)/* inputs */
                 );
- cpu_reset:
-#if 0
-        //CPU reset will reset memtroller ???
-        asm volatile ("jmp __cpu_reset" 
-                : /* outputs */ 
-                : "a"(bist) /* inputs */
-                );
-#endif
 
  fallback_image:
-        real_main(bist);
+	;
 }
-void real_main(unsigned long bist)
-#else
-void amd64_main(unsigned long bist)
 #endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	static const struct mem_controller cpu[] = {
+
-#if FIRST_CPU
+#if USE_FALLBACK_IMAGE == 1
-		{
+        failover_process(bist, cpu_init_detectedx);
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
 #endif
-#if SECOND_CPU
+        real_main(bist, cpu_init_detectedx);
-		{
+
-			.node_id = 1,
+}
-			.f0 = PCI_DEV(0, 0x19, 0),
+
-			.f1 = PCI_DEV(0, 0x19, 1),
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-			.f2 = PCI_DEV(0, 0x19, 2),
+{
-			.f3 = PCI_DEV(0, 0x19, 3),
+	static const uint16_t spd_addr [] = {
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
+			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
+			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
-		},
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
+			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
 #endif
 	};
 
         int needs_reset;
 	unsigned cpu_reset = 0;
+        unsigned bsp_apicid = 0;
+
+        struct mem_controller ctrl[8];
+        unsigned nodes;
 
         if (bist == 0) {
-#if CONFIG_LOGICAL_CPUS==1
+                bsp_apicid = init_cpus(cpu_init_detectedx);
-                struct node_core_id id;
-#else
-                unsigned nodeid;
-#endif
-                /* Skip this if there was a built in self test failure */
-//                amd_early_mtrr_init(); # don't need, already done in cache_as_ram
-
-#if CONFIG_LOGICAL_CPUS==1
-                set_apicid_cpuid_lo();
-                id = get_node_core_id_x(); // that is initid
-#else
-                nodeid = get_node_id();
-#endif
-
-                enable_lapic();
-//                init_timer();
-
-#if CONFIG_LOGICAL_CPUS==1
-                if(id.coreid == 0) {
-                        if (cpu_init_detected(id.nodeid)) {
-                                cpu_reset = 1;
-                                goto cpu_reset_x;
-                        }
-                        distinguish_cpu_resets(id.nodeid);
-//                        start_other_core(id.nodeid);
-                }
-#else
-                if (cpu_init_detected(nodeid)) {
-                                cpu_reset = 1;
-                                goto cpu_reset_x;
-                }
-                distinguish_cpu_resets(nodeid);
-#endif
-
-
-                if (!boot_cpu()
-#if CONFIG_LOGICAL_CPUS==1 
-                        || (id.coreid != 0)
-#endif
-                ) {
-                        // We need stop the CACHE as RAM for this CPU too
-                        #include "cpu/amd/car/cache_as_ram_post.c"
-                        stop_this_cpu(); // it will stop all cores except core0 of cpu0
-                }
-
         }
 
-	init_timer(); // only do it it first CPU
-
-	
  	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
         console_init();
@@ -301,9 +220,12 @@ void amd64_main(unsigned long bist)
 	
 #if CONFIG_LOGICAL_CPUS==1
         // It is said that we should start core1 after all core0 launched
+	wait_all_core0_started();
         start_other_cores();
 #endif
-	// automatically set that for you, but you might meet tight space
+
+        wait_all_aps_started(bsp_apicid);
+
         needs_reset |= ht_setup_chains_x();
 
         needs_reset |= ck804_early_setup_x();
@@ -313,93 +235,16 @@ void amd64_main(unsigned long bist)
                	soft_reset();
        	}
 
+        allow_all_aps_stop(bsp_apicid);
+
+        nodes = get_nodes();
+        //It's the time to set ctrl now;
+        fill_mem_ctrl(nodes, ctrl, spd_addr);
+
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(nodes, ctrl);
-
-#if 1
-        {
-        	/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
-	        unsigned v_esp;
-	        __asm__ volatile (
-        	        "movl   %%esp, %0\n\t"
-	                : "=a" (v_esp)
-	        );
-#if CONFIG_USE_INIT
-	        printk_debug("v_esp=%08x\r\n", v_esp);
-#else
-	        print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
-#endif
-        }
-
-#endif
-#if 1
-
-cpu_reset_x:
-
-#if CONFIG_USE_INIT
-        printk_debug("cpu_reset = %08x\r\n",cpu_reset);
-#else
-        print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
-#endif
-
-	if(cpu_reset == 0) {
-	        print_debug("Clearing initial memory region: ");
-	}
-	print_debug("No cache as ram now - ");
-
-	/* store cpu_reset to ebx */
-        __asm__ volatile (
-                "movl %0, %%ebx\n\t"
-                ::"a" (cpu_reset)
-        );
-
-	if(cpu_reset==0) {
-#define CLEAR_FIRST_1M_RAM 1
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-	else {
-#undef CLEAR_FIRST_1M_RAM 
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-
-	__asm__ volatile (
-                /* set new esp */ /* before _RAMBASE */
-                "subl   %0, %%ebp\n\t"
-                "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
-	);
-
-	{
-		unsigned new_cpu_reset;
-
-		/* get back cpu_reset from ebx */
-		__asm__ volatile (
-			"movl %%ebx, %0\n\t"
-			:"=a" (new_cpu_reset)
-		);
-		
-                /* We can not go back any more, we lost old stack data in cache as ram*/
-                if(new_cpu_reset==0) {
-                        print_debug("Use Ram as Stack now - done\r\n");
-                } else
-                {  
-                        print_debug("Use Ram as Stack now - \r\n");
-                }
-#if CONFIG_USE_INIT
-                printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
-#else
-                print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
-#endif
-	
-		/*copy and execute linuxbios_ram */
-		copy_and_run(new_cpu_reset);
-		/* We will not return */
-	}
-#endif
-
-
-	print_debug("should not be here -\r\n");
 
+	post_cache_as_ram(cpu_reset);
 }

src/mainboard/tyan/s2892/Config.lb

@@ -97,9 +97,12 @@ end
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
 
 if USE_DCACHE_RAM
 	if CONFIG_USE_INIT

src/mainboard/tyan/s2892/Options.lb

@@ -53,7 +53,7 @@ uses CONFIG_GDB_STUB
 uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses K8_E0_MEM_HOLE_SIZEK
+uses K8_HW_MEM_HOLE_SIZEK
 
 uses CK804_DEVN_BASE
 
@@ -73,7 +73,9 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=131072
+#256K
+default FALLBACK_SIZE=0x40000
 
 ###
 ### Build options
@@ -123,7 +125,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=2
 default CONFIG_LOGICAL_CPUS=1
 
 #1G memory hole
-default K8_E0_MEM_HOLE_SIZEK=0x100000
+default K8_HW_MEM_HOLE_SIZEK=0x100000
 
 #CK804 setting
 
@@ -139,10 +141,10 @@ default CONFIG_PCI_ROM_RUN=1
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=0
+default USE_DCACHE_RAM=1
 default DCACHE_RAM_BASE=0xcf000
 default DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
+default CONFIG_USE_INIT=1
 
 
 ##

src/mainboard/tyan/s2892/cache_as_ram_auto.c

@@ -14,7 +14,6 @@
 #include "ram/ramtest.c"
 
 #include "northbridge/amd/amdk8/cpu_rev.c"
-#define K8_HT_FREQ_1G_SUPPORT 0
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
@@ -85,14 +84,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
-#include "cpu/amd/dualcore/dualcore.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
 #endif
-
+#include "cpu/amd/dualcore/dualcore.c"
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 
 #define CK804_NUM 1
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
@@ -107,6 +100,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/car/copy_and_run.c"
 
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+
 #if USE_FALLBACK_IMAGE == 1
 
 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
@@ -129,38 +127,13 @@ static void sio_setup(void)
 
 
 }
-void real_main(unsigned long bist);
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-
-void amd64_main(unsigned long bist)
 {
-#if CONFIG_LOGICAL_CPUS==1
+        unsigned last_boot_normal_x = last_boot_normal();
-        struct node_core_id id;
-#else
-        unsigned nodeid;
-#endif
-        /* Make cerain my local apic is useable */
-//        enable_lapic();
 
-#if CONFIG_LOGICAL_CPUS==1
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        id = get_node_core_id_x();
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
-        /* Is this a cpu only reset? */
+                if (last_boot_normal_x) {
-        if (cpu_init_detected(id.nodeid)) {
-#else
-//        nodeid = lapicid() & 0xf;
-        nodeid = get_node_id();
-        /* Is this a cpu only reset? */
-        if (cpu_init_detected(nodeid)) {
-#endif
-                if (last_boot_normal()) {
-                        goto normal_image;
-                } else {
-                        goto cpu_reset;
-                }
-        }
-
-        /* Is this a secondary cpu? */
-        if (!boot_cpu()) {
-                if (last_boot_normal()) {
                         goto normal_image;
                 } else {
                         goto fallback_image;
@@ -178,7 +151,7 @@ void amd64_main(unsigned long bist)
         ck804_enable_rom();
 
         /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal()) {
+        if (bios_reset_detected() && last_boot_normal_x) {
                 goto normal_image;
         }
         /* This is the primary cpu how should I boot? */
@@ -191,27 +164,29 @@ void amd64_main(unsigned long bist)
  normal_image:
         __asm__ volatile ("jmp __normal_image"
                 : /* outputs */
-                : "a" (bist) /* inputs */
+                : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
-                );
- cpu_reset:
-#if 0
-        //CPU reset will reset memtroller ???
-        asm volatile ("jmp __cpu_reset" 
-                : /* outputs */ 
-                : "a"(bist) /* inputs */
                 );
+ 
+ fallback_image:
+	;
+}
 #endif
 
- fallback_image:
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-        real_main(bist);
+
-}
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-void real_main(unsigned long bist)
+{
-#else
+
-void amd64_main(unsigned long bist)
+#if USE_FALLBACK_IMAGE == 1
+        failover_process(bist, cpu_init_detectedx);
 #endif
+        real_main(bist, cpu_init_detectedx);
+
+}
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
 		{
 			.node_id = 0,
 			.f0 = PCI_DEV(0, 0x18, 0),
@@ -221,8 +196,7 @@ void amd64_main(unsigned long bist)
 			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 		},
-#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
-#if SECOND_CPU
 		{
 			.node_id = 1,
 			.f0 = PCI_DEV(0, 0x19, 0),
@@ -239,56 +213,9 @@ void amd64_main(unsigned long bist)
 	unsigned cpu_reset = 0;
 
         if (bist == 0) {
-#if CONFIG_LOGICAL_CPUS==1
+		init_cpus(cpu_init_detectedx);
-                struct node_core_id id;
-#else
-                unsigned nodeid;
-#endif
-                /* Skip this if there was a built in self test failure */
-//                amd_early_mtrr_init(); # don't need, already done in cache_as_ram
-
-#if CONFIG_LOGICAL_CPUS==1
-                set_apicid_cpuid_lo();
-                id = get_node_core_id_x(); // that is initid
-#else
-                nodeid = get_node_id();
-#endif
-
-                enable_lapic();
-//                init_timer();
-
-#if CONFIG_LOGICAL_CPUS==1
-                if(id.coreid == 0) {
-                        if (cpu_init_detected(id.nodeid)) {
-                                cpu_reset = 1;
-                                goto cpu_reset_x;
-                        }
-                        distinguish_cpu_resets(id.nodeid);
-                }
-#else
-                if (cpu_init_detected(nodeid)) {
-                                cpu_reset = 1;
-                                goto cpu_reset_x;
-                }
-                distinguish_cpu_resets(nodeid);
-#endif
-
-
-                if (!boot_cpu()
-#if CONFIG_LOGICAL_CPUS==1 
-                        || (id.coreid != 0)
-#endif
-                ) {
-                        // We need stop the CACHE as RAM for this CPU too
-                        #include "cpu/amd/car/cache_as_ram_post.c"
-                        stop_this_cpu(); // it will stop all cores except core0 of cpu0
-                }
-
         }
 
-	init_timer(); // only do it it first CPU
-
-	
  	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
         console_init();
@@ -301,8 +228,10 @@ void amd64_main(unsigned long bist)
 	needs_reset = setup_coherent_ht_domain();
 	
 #if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
         start_other_cores();
 #endif
+
         needs_reset |= ht_setup_chains_x();
 
         needs_reset |= ck804_early_setup_x();
@@ -317,89 +246,5 @@ void amd64_main(unsigned long bist)
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
-
+	post_cache_as_ram(cpu_reset);
-#if 1
-        {
-        	/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
-	        unsigned v_esp;
-	        __asm__ volatile (
-        	        "movl   %%esp, %0\n\t"
-	                : "=a" (v_esp)
-	        );
-#if CONFIG_USE_INIT
-	        printk_debug("v_esp=%08x\r\n", v_esp);
-#else
-	        print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
-#endif
-        }
-
-#endif
-#if 1
-
-cpu_reset_x:
-
-#if CONFIG_USE_INIT
-        printk_debug("cpu_reset = %08x\r\n",cpu_reset);
-#else
-        print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
-#endif
-
-	if(cpu_reset == 0) {
-	        print_debug("Clearing initial memory region: ");
-	}
-	print_debug("No cache as ram now - ");
-
-	/* store cpu_reset to ebx */
-        __asm__ volatile (
-                "movl %0, %%ebx\n\t"
-                ::"a" (cpu_reset)
-        );
-
-	if(cpu_reset==0) {
-#define CLEAR_FIRST_1M_RAM 1
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-	else {
-#undef CLEAR_FIRST_1M_RAM 
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-
-	__asm__ volatile (
-                /* set new esp */ /* before _RAMBASE */
-                "subl   %0, %%ebp\n\t"
-                "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
-	);
-
-	{
-		unsigned new_cpu_reset;
-
-		/* get back cpu_reset from ebx */
-		__asm__ volatile (
-			"movl %%ebx, %0\n\t"
-			:"=a" (new_cpu_reset)
-		);
-
-		/* We can not go back any more, we lost old stack data in cache as ram*/
-		if(new_cpu_reset==0) {        
-		        print_debug("Use Ram as Stack now - done\r\n");	
-		} else 
-		{	
-			print_debug("Use Ram as Stack now - \r\n");
-		}
-#if CONFIG_USE_INIT
-                printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
-#else
-                print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
-#endif
-	
-		/*copy and execute linuxbios_ram */
-		copy_and_run(new_cpu_reset);
-		/* We will not return */
-	}
-#endif
-
-
-	print_debug("should not be here -\r\n");
-
 }

src/mainboard/tyan/s2895/Config.lb

@@ -89,9 +89,13 @@ end
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
+
 if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds

src/mainboard/tyan/s2895/Options.lb

@@ -52,7 +52,8 @@ uses CONFIG_GDB_STUB
 uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses K8_E0_MEM_HOLE_SIZEK
+uses K8_HW_MEM_HOLE_SIZEK
+uses K8_HT_FREQ_1G_SUPPORT
 
 uses CK804_DEVN_BASE
 
@@ -61,6 +62,10 @@ uses DCACHE_RAM_BASE
 uses DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 
+uses ENABLE_APIC_EXT_ID
+uses APIC_ID_OFFSET
+uses LIFT_BSP_APIC_ID
+
 ## ROM_SIZE is the size of boot ROM that this board will use.
 #512K bytes 
 default ROM_SIZE=524288
@@ -71,7 +76,9 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=131072
+#256K
+default FALLBACK_SIZE=0x40000
 
 ###
 ### Build options
@@ -124,7 +131,10 @@ default CONFIG_LOGICAL_CPUS=1
 #default CONFIG_CHIP_NAME=1
 
 #1G memory hole
-default K8_E0_MEM_HOLE_SIZEK=0x100000
+default K8_HW_MEM_HOLE_SIZEK=0x100000
+
+#Opteron K8 1G HT Support
+default K8_HT_FREQ_1G_SUPPORT=1
 
 #CK804 setting
 #default CK804_DEVN_BASE=0
@@ -141,6 +151,11 @@ default DCACHE_RAM_BASE=0xcf000
 default DCACHE_RAM_SIZE=0x1000
 default CONFIG_USE_INIT=1
 
+default ENABLE_APIC_EXT_ID=1
+default APIC_ID_OFFSET=0x10
+default LIFT_BSP_APIC_ID=0
+
+
 ##
 ## Build code to setup a generic IOAPIC
 ##

src/mainboard/tyan/s2895/cache_as_ram_auto.c

@@ -1,5 +1,17 @@
 #define ASSEMBLY 1
 #define __ROMCC__
+
+
+#define K8_ALLOCATE_IO_RANGE 1
+//#define K8_SCAN_PCI_BUS 1
+
+
+#define K8_4RANK_DIMM_SUPPORT 1
+
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
+
  
 #include <stdint.h>
 #include <device/pci_def.h>
@@ -14,9 +26,6 @@
 #include "ram/ramtest.c"
 
 #include "northbridge/amd/amdk8/cpu_rev.c"
-#define K8_HT_FREQ_1G_SUPPORT 1
-#define K8_ALLOCATE_IO_RANGE 1
-//#define K8_SCAN_PCI_BUS 1
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
@@ -76,8 +85,7 @@ static void sio_gpio_setup(void){
 
         unsigned value;
 
-//      lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c
+        /*Enable onboard scsi*/
-
         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L 
         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
@@ -94,16 +102,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-#define K8_4RANK_DIMM_SUPPORT 1
 
 #include "northbridge/amd/amdk8/raminit.c"
-#if 0
-        #define ENABLE_APIC_EXT_ID 1
-        #define APIC_ID_OFFSET 0x10
-        #define LIFT_BSP_APIC_ID 0
-#else
-        #define ENABLE_APIC_EXT_ID 0
-#endif
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "sdram/generic_sdram.c"
 
@@ -112,10 +112,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
 #define CK804_NUM 2
 #define CK804B_BUSN 0x80
 #define CK804_USE_NIC 1
@@ -140,6 +136,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/model_fxx/init_cpus.c"
 
+
 #if USE_FALLBACK_IMAGE == 1
 
 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
@@ -154,18 +151,13 @@ static void sio_setup(void)
         uint8_t byte;
 
         
-        /* LPC Variable Range Decode 1 0x400-0x47f */
-        /* to make sure lpc47b397 gpio on device work */
         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
         
-        /* subject decoding*/
         byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
         byte |= 0x20; 
         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
         
-        /* LPC Positive Decode 0 */
         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
-        /*decode VAR1, serial 0 */
         dword |= (1<<29)|(1<<0);
         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
         
@@ -179,22 +171,13 @@ static void sio_setup(void)
 
 }
 
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-
-void amd64_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-        /* Is this a cpu only reset? */
+        unsigned last_boot_normal_x = last_boot_normal();
-        if (cpu_init_detectedx) {
-                if (last_boot_normal()) {
-                        goto normal_image;
-                } else {
-                        goto cpu_reset;
-                }
-        }
 
-        /* Is this a secondary cpu? */
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        if (!boot_cpu()) {
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
-                if (last_boot_normal()) {
+                if (last_boot_normal_x) {
                         goto normal_image;
                 } else {
                         goto fallback_image;
@@ -212,7 +195,7 @@ void amd64_main(unsigned long bist, unsigned long cpu_init_detectedx)
         ck804_enable_rom();
 
         /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal()) {
+        if (bios_reset_detected() && last_boot_normal_x) {
                 goto normal_image;
         }
         /* This is the primary cpu how should I boot? */
@@ -227,54 +210,44 @@ void amd64_main(unsigned long bist, unsigned long cpu_init_detectedx)
                 : /* outputs */
                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
                 );
- cpu_reset:
-#if 0
-        //CPU reset will reset memtroller ???
-        asm volatile ("jmp __cpu_reset" 
-                : /* outputs */ 
-                : "a"(bist) /* inputs */
-                );
-#endif
 
  fallback_image:
-        real_main(bist, cpu_init_detectedx);
+	;
 }
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-#else
-void amd64_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	static const struct mem_controller cpu[] = {
+
-#if FIRST_CPU
+#if USE_FALLBACK_IMAGE == 1
-		{
+        failover_process(bist, cpu_init_detectedx);
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
 #endif
-#if SECOND_CPU
+        real_main(bist, cpu_init_detectedx);
-		{
+
-			.node_id = 1,
+}
-			.f0 = PCI_DEV(0, 0x19, 0),
+
-			.f1 = PCI_DEV(0, 0x19, 1),
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-			.f2 = PCI_DEV(0, 0x19, 2),
+{
-			.f3 = PCI_DEV(0, 0x19, 3),
+	static const uint16_t spd_addr [] = {
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
+			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
+			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
-		},
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
+			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
 #endif
 	};
 
         int needs_reset;
-
 	unsigned cpu_reset = 0;
+        unsigned bsp_apicid = 0;
+
+        struct mem_controller ctrl[8];
+        unsigned nodes;
 
         if (bist == 0) {
-		init_cpus(cpu_init_detectedx, sizeof(cpu)/sizeof(cpu[0]), cpu);
+                bsp_apicid = init_cpus(cpu_init_detectedx);
         }
 
 	lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
@@ -288,6 +261,14 @@ void amd64_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	needs_reset = setup_coherent_ht_domain();
 
+#if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
+	wait_all_core0_started();
+        start_other_cores();
+#endif
+
+        wait_all_aps_started(bsp_apicid);
+
         needs_reset |= ht_setup_chains_x();
 
         needs_reset |= ck804_early_setup_x();
@@ -297,11 +278,16 @@ void amd64_main(unsigned long bist, unsigned long cpu_init_detectedx)
                	soft_reset();
        	}
 
+        allow_all_aps_stop(bsp_apicid);
+
+        nodes = get_nodes();
+        //It's the time to set ctrl now;
+        fill_mem_ctrl(nodes, ctrl, spd_addr);
+
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(nodes, ctrl);
-	
-	post_cache_as_ram(cpu_reset);
 
+	post_cache_as_ram(cpu_reset);
 }

src/mainboard/tyan/s4880/Config.lb

@@ -103,9 +103,13 @@ end
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
+
 if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
@@ -204,11 +208,11 @@ chip northbridge/amd/amdk8/root_complex
 				chip southbridge/amd/amd8131
 					# the on/off keyword is mandatory
                                         device pci 0.0 on
-#                                                chip drivers/lsi/53c1030
+                                                chip drivers/lsi/53c1030
-#                                                        device pci 4.0 on end
+                                                        device pci 4.0 on end
-#                                                        device pci 4.1 on end
+                                                        device pci 4.1 on end
-#                                                        register "fw_address" = "0xfff8c000"
+                                                        register "fw_address" = "0xfff8c000"
-#                                                end
+                                                end
                                                 chip drivers/pci/onboard
                                                         device pci 9.0 on end
                                                         device pci 9.1 on end

src/mainboard/tyan/s4880/Options.lb

@@ -52,13 +52,17 @@ uses OBJCOPY
 uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses K8_E0_MEM_HOLE_SIZEK
+uses K8_HW_MEM_HOLE_SIZEK
 
 uses USE_DCACHE_RAM
 uses DCACHE_RAM_BASE
 uses DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 
+uses ENABLE_APIC_EXT_ID
+uses APIC_ID_OFFSET
+uses LIFT_BSP_APIC_ID
+
 ###
 ### Build options
 ###
@@ -71,7 +75,9 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=131072
+#256K
+default FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot
@@ -120,7 +126,7 @@ default CONFIG_LOGICAL_CPUS=1
 default CONFIG_CHIP_NAME=1
 
 #1G memory hole
-default K8_E0_MEM_HOLE_SIZEK=0x100000
+default K8_HW_MEM_HOLE_SIZEK=0x100000
 
 #VGA Console
 default CONFIG_CONSOLE_VGA=1
@@ -130,10 +136,15 @@ default CONFIG_PCI_ROM_RUN=1
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=0
+default USE_DCACHE_RAM=1
 default DCACHE_RAM_BASE=0xcf000
 default DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
+default CONFIG_USE_INIT=1
+
+default ENABLE_APIC_EXT_ID=1
+default APIC_ID_OFFSET=0x10
+default LIFT_BSP_APIC_ID=0
+
 
 ##
 ## Build code to setup a generic IOAPIC

src/mainboard/tyan/s4880/cache_as_ram_auto.c

@@ -14,7 +14,6 @@
 #include "ram/ramtest.c"
 
 #include "northbridge/amd/amdk8/cpu_rev.c"
-#define K8_HT_FREQ_1G_SUPPORT 0
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
@@ -37,28 +36,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
-
 static void hard_reset(void)
 {
         device_t dev;
@@ -112,6 +89,18 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
         smbus_write_byte(SMBUS_HUB, 0x01, device);
         smbus_write_byte(SMBUS_HUB, 0x03, 0);
 }
+#if 0
+static inline void change_i2c_mux(unsigned device)
+{
+#define SMBUS_HUB 0x18
+        int ret;
+        print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); 
+        ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
+        print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
+        ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
+        print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
+}
+#endif
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
@@ -121,13 +110,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define K8_4RANK_DIMM_SUPPORT 1
 
 #include "northbridge/amd/amdk8/raminit.c"
-#if 0
-        #define ENABLE_APIC_EXT_ID 1
-        #define APIC_ID_OFFSET 0x10
-        #define LIFT_BSP_APIC_ID 0
-#else 
-        #define ENABLE_APIC_EXT_ID 0
-#endif
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "sdram/generic_sdram.c"
 
@@ -136,17 +118,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
-#include "cpu/amd/dualcore/dualcore.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
 #endif
-#define FIRST_CPU  1
+#include "cpu/amd/dualcore/dualcore.c"
-#define SECOND_CPU 1
-
-#define THIRD_CPU  1 
-#define FOURTH_CPU 1 
-
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU)
 
 #define RC0 ((1<<2)<<8)
 #define RC1 ((1<<1)<<8)
@@ -160,43 +133,23 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/car/copy_and_run.c"
 
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+
 #if USE_FALLBACK_IMAGE == 1
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-void real_main(unsigned long bist);
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-
-void amd64_main(unsigned long bist)
 {
-#if CONFIG_LOGICAL_CPUS==1
+        unsigned last_boot_normal_x = last_boot_normal();
-        struct node_core_id id;
-#else
-        unsigned nodeid;
-#endif
-        /* Make cerain my local apic is useable */
-//        enable_lapic();
 
-#if CONFIG_LOGICAL_CPUS==1
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        id = get_node_core_id_x();
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
-        /* Is this a cpu only reset? */
+                if (last_boot_normal_x) {
-        if (cpu_init_detected(id.nodeid)) {
-#else
-//        nodeid = lapicid();
-	nodeid = get_node_id();
-        /* Is this a cpu only reset? */
-        if (cpu_init_detected(nodeid)) {
-#endif
-                if (last_boot_normal()) {
-                        goto normal_image;
-                } else {
-                        goto cpu_reset;
-                }
-        }
-
-        /* Is this a secondary cpu? */
-        if (!boot_cpu()) {
-                if (last_boot_normal()) {
                         goto normal_image;
                 } else {
                         goto fallback_image;
@@ -208,11 +161,10 @@ void amd64_main(unsigned long bist)
 
         enumerate_ht_chain();
 
-        /* Setup the ck804 */
         amd8111_enable_rom();
 
         /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal()) {
+        if (bios_reset_detected() && last_boot_normal_x) {
                 goto normal_image;
         }
         /* This is the primary cpu how should I boot? */
@@ -225,27 +177,29 @@ void amd64_main(unsigned long bist)
  normal_image:
         __asm__ volatile ("jmp __normal_image"
                 : /* outputs */
-                : "a" (bist) /* inputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
                 );
- cpu_reset:
-#if 0
-        //CPU reset will reset memtroller ???
-        asm volatile ("jmp __cpu_reset" 
-                : /* outputs */ 
-                : "a"(bist) /* inputs */
-                );
-#endif
 
  fallback_image:
-        real_main(bist);
+	;
 }
-void real_main(unsigned long bist)
-#else
-void amd64_main(unsigned long bist)
 #endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+
+#if USE_FALLBACK_IMAGE == 1
+        failover_process(bist, cpu_init_detectedx);
+#endif
+        real_main(bist, cpu_init_detectedx);
+
+}
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
                 {
                         .node_id = 0,
                         .f0 = PCI_DEV(0, 0x18, 0),
@@ -255,8 +209,7 @@ void amd64_main(unsigned long bist)
                         .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
                         .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
                 },
-#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
-#if SECOND_CPU
                 {
                         .node_id = 1,
                         .f0 = PCI_DEV(0, 0x19, 0),
@@ -269,7 +222,7 @@ void amd64_main(unsigned long bist)
                 },
 #endif
 
-#if THIRD_CPU
+#if CONFIG_MAX_PHYSICAL_CPUS > 2
                 {
                         .node_id = 2,
                         .f0 = PCI_DEV(0, 0x1a, 0),
@@ -280,8 +233,6 @@ void amd64_main(unsigned long bist)
                         .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
 
                 },
-#endif
-#if FOURTH_CPU
                 {
                         .node_id = 3,
                         .f0 = PCI_DEV(0, 0x1b, 0),
@@ -299,75 +250,9 @@ void amd64_main(unsigned long bist)
 	unsigned cpu_reset = 0;
 
         if (bist == 0) {
-#if CONFIG_LOGICAL_CPUS==1
+		init_cpus(cpu_init_detectedx);
-        	struct node_core_id id;
-#else
-	        unsigned nodeid;
-#endif
-                /* Skip this if there was a built in self test failure */
-//                amd_early_mtrr_init(); # don't need, already done in cache_as_ram
-
-#if CONFIG_LOGICAL_CPUS==1
-                set_apicid_cpuid_lo();
-		id = get_node_core_id_x(); // that is initid
-        #if ENABLE_APIC_EXT_ID == 1
-                if(id.coreid == 0) {
-                        enable_apic_ext_id(id.nodeid);
-                }
-        #endif
-#else
-                nodeid = get_node_id();
-        #if ENABLE_APIC_EXT_ID == 1
-                enable_apic_ext_id(nodeid);
-        #endif
-#endif
-
-                enable_lapic();
-                init_timer();
-
-//                post_code(0x30);
-
-#if CONFIG_LOGICAL_CPUS==1
-        #if ENABLE_APIC_EXT_ID == 1
-            #if LIFT_BSP_APIC_ID == 0
-                if( id.nodeid != 0 ) //all except cores in node0
-            #endif
-                        lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) );
-        #endif
-                if(id.coreid == 0) {
-                        if (cpu_init_detected(id.nodeid)) {
-				cpu_reset = 1;
-				goto cpu_reset_x;
-                        }
-                        distinguish_cpu_resets(id.nodeid);
-                }
-#else
-        #if ENABLE_APIC_EXT_ID == 1
-            #if LIFT_BSP_APIC_ID == 0
-                if(nodeid != 0)
-            #endif
-                        lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10
-
-        #endif
-                if (cpu_init_detected(nodeid)) {
-			cpu_reset = 1;
-			goto cpu_reset_x;
-                }
-                distinguish_cpu_resets(nodeid);
-#endif
-
-                if (!boot_cpu()
-#if CONFIG_LOGICAL_CPUS==1 
-                        || (id.coreid != 0)
-#endif
-                ) {
-			// We need stop the CACHE as RAM for this CPU too
-			#include "cpu/amd/car/cache_as_ram_post.c"
-                        stop_this_cpu(); // it will stop all cores except core0 of cpu0
-                }
         }
 
-	
  	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
         console_init();
@@ -383,6 +268,7 @@ void amd64_main(unsigned long bist)
         // It is said that we should start core1 after all core0 launched
         start_other_cores();
 #endif
+	// automatically set that for you, but you might meet tight space
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
@@ -395,90 +281,5 @@ void amd64_main(unsigned long bist)
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
-
+	post_cache_as_ram(cpu_reset);
-#if 1
-        {
-        /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
-        unsigned v_esp;
-        __asm__ volatile (
-                "movl   %%esp, %0\n\t"
-                : "=a" (v_esp)
-        );
-#if CONFIG_USE_INIT
-        printk_debug("v_esp=%08x\r\n", v_esp);
-#else           
-        print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
-#endif    
-        }
-#endif
-
-#if 1
-
-
-cpu_reset_x:
-
-#if CONFIG_USE_INIT
-        printk_debug("cpu_reset = %08x\r\n",cpu_reset);
-#else
-        print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
-#endif
-
-	if(cpu_reset == 0) {
-	        print_debug("Clearing initial memory region: ");
-	}
-	print_debug("No cache as ram now - ");
-
-	/* store cpu_reset to ebx */
-        __asm__ volatile (
-                "movl %0, %%ebx\n\t"
-                ::"a" (cpu_reset)
-        );
-
-	if(cpu_reset==0) {
-#define CLEAR_FIRST_1M_RAM 1
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-	else {
-#undef CLEAR_FIRST_1M_RAM 
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-
-	__asm__ volatile (
-                /* set new esp */ /* before _RAMBASE */
-                "subl   %0, %%ebp\n\t"
-                "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
-	);
-
-	{
-		unsigned new_cpu_reset;
-
-		/* get back cpu_reset from ebx */
-		__asm__ volatile (
-			"movl %%ebx, %0\n\t"
-			:"=a" (new_cpu_reset)
-		);
-
-		print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
-		if(new_cpu_reset==0) {        
-		        print_debug("done\r\n");	
-		} else 
-		{	
-			print_debug("\r\n");
-		}
-
-#if CONFIG_USE_INIT
-                printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
-#else
-                print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
-#endif
-		/*copy and execute linuxbios_ram */
-		copy_and_run(new_cpu_reset);
-		/* We will not return */
-	}
-#endif
-
-
-	print_debug("should not be here -\r\n");
-
 }

src/mainboard/tyan/s4882/Config.lb

@@ -103,9 +103,13 @@ end
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
+
 if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds

src/mainboard/tyan/s4882/Options.lb

@@ -52,13 +52,17 @@ uses OBJCOPY
 uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses K8_E0_MEM_HOLE_SIZEK
+uses K8_HW_MEM_HOLE_SIZEK
 
 uses USE_DCACHE_RAM
 uses DCACHE_RAM_BASE
 uses DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 
+uses ENABLE_APIC_EXT_ID
+uses APIC_ID_OFFSET
+uses LIFT_BSP_APIC_ID
+
 ###
 ### Build options
 ###
@@ -71,7 +75,9 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=131072
+#256K
+default FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot
@@ -120,20 +126,24 @@ default CONFIG_LOGICAL_CPUS=1
 default CONFIG_CHIP_NAME=1
 
 #1G memory hole
-default K8_E0_MEM_HOLE_SIZEK=0x100000
+default K8_HW_MEM_HOLE_SIZEK=0x100000
 
 #VGA Console
-default CONFIG_CONSOLE_VGA=1
+#default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
+#default CONFIG_PCI_ROM_RUN=1
 
 
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=0
+default USE_DCACHE_RAM=1
 default DCACHE_RAM_BASE=0xcf000
 default DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
+default CONFIG_USE_INIT=1
+
+default ENABLE_APIC_EXT_ID=1
+default APIC_ID_OFFSET=0x10
+default LIFT_BSP_APIC_ID=0
 
 ##
 ## Build code to setup a generic IOAPIC
@@ -173,7 +183,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 ##
 ## LinuxBIOS C code runs at this location in RAM
 ##
-default _RAMBASE=0x00004000
+default _RAMBASE=0x00002000
 
 ##
 ## Load the payload from the ROM

src/mainboard/tyan/s4882/cache_as_ram_auto.c

@@ -14,7 +14,6 @@
 #include "ram/ramtest.c"
 
 #include "northbridge/amd/amdk8/cpu_rev.c"
-#define K8_HT_FREQ_1G_SUPPORT 0
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
@@ -37,28 +36,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
-
 static void hard_reset(void)
 {
         device_t dev;
@@ -117,6 +94,21 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
 
         smbus_write_byte(SMBUS_HUB, 0x03, 0);
 }
+#if 0
+static inline void change_i2c_mux(unsigned device)
+{
+#define SMBUS_HUB 0x18
+        int ret, i;
+        print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); 
+        i=2;
+        do {
+                ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
+                print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
+        } while ((ret!=0) && (i-->0));
+        ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
+        print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
+}
+#endif
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
@@ -126,13 +118,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define K8_4RANK_DIMM_SUPPORT 1
 
 #include "northbridge/amd/amdk8/raminit.c"
-#if 0
-        #define ENABLE_APIC_EXT_ID 1
-        #define APIC_ID_OFFSET 0x10
-        #define LIFT_BSP_APIC_ID 0
-#else 
-        #define ENABLE_APIC_EXT_ID 0
-#endif
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "sdram/generic_sdram.c"
 
@@ -141,17 +126,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
-#include "cpu/amd/dualcore/dualcore.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
 #endif
-#define FIRST_CPU  1
+#include "cpu/amd/dualcore/dualcore.c"
-#define SECOND_CPU 1
-
-#define THIRD_CPU  1 
-#define FOURTH_CPU 1 
-
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU)
 
 #define RC0 ((1<<2)<<8)
 #define RC1 ((1<<1)<<8)
@@ -165,43 +141,22 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/car/copy_and_run.c"
 
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
 #if USE_FALLBACK_IMAGE == 1
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-void real_main(unsigned long bist);
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-
-void amd64_main(unsigned long bist)
 {
-#if CONFIG_LOGICAL_CPUS==1
+        unsigned last_boot_normal_x = last_boot_normal();
-        struct node_core_id id;
-#else
-        unsigned nodeid;
-#endif
-        /* Make cerain my local apic is useable */
-//        enable_lapic();
 
-#if CONFIG_LOGICAL_CPUS==1
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        id = get_node_core_id_x();
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
-        /* Is this a cpu only reset? */
+                if (last_boot_normal_x) {
-        if (cpu_init_detected(id.nodeid)) {
-#else
-//        nodeid = lapicid();
-	nodeid = get_node_id();
-        /* Is this a cpu only reset? */
-        if (cpu_init_detected(nodeid)) {
-#endif
-                if (last_boot_normal()) {
-                        goto normal_image;
-                } else {
-                        goto cpu_reset;
-                }
-        }
-
-        /* Is this a secondary cpu? */
-        if (!boot_cpu()) {
-                if (last_boot_normal()) {
                         goto normal_image;
                 } else {
                         goto fallback_image;
@@ -213,11 +168,10 @@ void amd64_main(unsigned long bist)
 
         enumerate_ht_chain();
 
-        /* Setup the ck804 */
         amd8111_enable_rom();
 
         /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal()) {
+        if (bios_reset_detected() && last_boot_normal_x) {
                 goto normal_image;
         }
         /* This is the primary cpu how should I boot? */
@@ -230,147 +184,55 @@ void amd64_main(unsigned long bist)
  normal_image:
         __asm__ volatile ("jmp __normal_image"
                 : /* outputs */
-                : "a" (bist) /* inputs */
+                : "a" (bist), "b" ( cpu_init_detectedx ) /* inputs */
                 );
- cpu_reset:
-#if 0
-        //CPU reset will reset memtroller ???
-        asm volatile ("jmp __cpu_reset" 
-                : /* outputs */ 
-                : "a"(bist) /* inputs */
-                );
-#endif
 
  fallback_image:
-        real_main(bist);
+	;
 }
-void real_main(unsigned long bist)
-#else
-void amd64_main(unsigned long bist)
 #endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	static const struct mem_controller cpu[] = {
+
-#if FIRST_CPU
+#if USE_FALLBACK_IMAGE == 1
-                {
+        failover_process(bist, cpu_init_detectedx);
-                        .node_id = 0,
-                        .f0 = PCI_DEV(0, 0x18, 0),
-                        .f1 = PCI_DEV(0, 0x18, 1),
-                        .f2 = PCI_DEV(0, 0x18, 2),
-                        .f3 = PCI_DEV(0, 0x18, 3),
-                        .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
-                        .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
-                },
 #endif
-#if SECOND_CPU
+        real_main(bist, cpu_init_detectedx);
-                {
-                        .node_id = 1,
-                        .f0 = PCI_DEV(0, 0x19, 0),
-                        .f1 = PCI_DEV(0, 0x19, 1),
-                        .f2 = PCI_DEV(0, 0x19, 2),
-                        .f3 = PCI_DEV(0, 0x19, 3),
-                        .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 },
-                        .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 },
 
-                },
+}
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	static const uint16_t spd_addr [] = {
+                        RC0|DIMM0, RC0|DIMM2, 0, 0,
+                        RC0|DIMM1, RC0|DIMM3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+                        RC1|DIMM0, RC1|DIMM2, 0, 0,
+                        RC1|DIMM1, RC1|DIMM3, 0, 0,
 #endif
-
+#if CONFIG_MAX_PHYSICAL_CPUS > 2
-#if THIRD_CPU
+                        RC2|DIMM0, RC2|DIMM2, 0, 0,
-                {
+                        RC2|DIMM1, RC2|DIMM3, 0, 0,
-                        .node_id = 2,
+                        RC3|DIMM0, RC3|DIMM2, 0, 0,
-                        .f0 = PCI_DEV(0, 0x1a, 0),
+                        RC3|DIMM1, RC3|DIMM3, 0, 0,
-                        .f1 = PCI_DEV(0, 0x1a, 1),
-                        .f2 = PCI_DEV(0, 0x1a, 2),
-                        .f3 = PCI_DEV(0, 0x1a, 3),
-                        .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
-                        .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
-
-                },
-#endif
-#if FOURTH_CPU
-                {
-                        .node_id = 3,
-                        .f0 = PCI_DEV(0, 0x1b, 0),
-                        .f1 = PCI_DEV(0, 0x1b, 1),
-                        .f2 = PCI_DEV(0, 0x1b, 2),
-                        .f3 = PCI_DEV(0, 0x1b, 3),
-                        .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
-                        .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
-
-                },
 #endif
 	};
 
         int needs_reset;
 	unsigned cpu_reset = 0;
+        unsigned bsp_apicid = 0;
+
+        struct mem_controller ctrl[8];
+        unsigned nodes;
 
         if (bist == 0) {
-#if CONFIG_LOGICAL_CPUS==1
+                bsp_apicid = init_cpus(cpu_init_detectedx);
-        	struct node_core_id id;
-#else
-	        unsigned nodeid;
-#endif
-                /* Skip this if there was a built in self test failure */
-//                amd_early_mtrr_init(); # don't need, already done in cache_as_ram
-
-#if CONFIG_LOGICAL_CPUS==1
-                set_apicid_cpuid_lo();
-		id = get_node_core_id_x(); // that is initid
-        #if ENABLE_APIC_EXT_ID == 1
-                if(id.coreid == 0) {
-                        enable_apic_ext_id(id.nodeid);
-                }
-        #endif
-#else
-                nodeid = get_node_id();
-        #if ENABLE_APIC_EXT_ID == 1
-                enable_apic_ext_id(nodeid);
-        #endif
-#endif
-
-                enable_lapic();
-                init_timer();
-
-
-#if CONFIG_LOGICAL_CPUS==1
-        #if ENABLE_APIC_EXT_ID == 1
-            #if LIFT_BSP_APIC_ID == 0
-                if( id.nodeid != 0 ) //all except cores in node0
-            #endif
-                        lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) );
-        #endif
-                if(id.coreid == 0) {
-                        if (cpu_init_detected(id.nodeid)) {
-				cpu_reset = 1;
-				goto cpu_reset_x;
-                        }
-                        distinguish_cpu_resets(id.nodeid);
-                }
-#else
-        #if ENABLE_APIC_EXT_ID == 1
-            #if LIFT_BSP_APIC_ID == 0
-                if(nodeid != 0)
-            #endif
-                        lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10
-
-        #endif
-                if (cpu_init_detected(nodeid)) {
-			cpu_reset = 1;
-			goto cpu_reset_x;
-                }
-                distinguish_cpu_resets(nodeid);
-#endif
-
-                if (!boot_cpu()
-#if CONFIG_LOGICAL_CPUS==1 
-                        || (id.coreid != 0)
-#endif
-                ) {
-			// We need stop the CACHE as RAM for this CPU too
-			#include "cpu/amd/car/cache_as_ram_post.c"
-                        stop_this_cpu(); // it will stop all cores except core0 of cpu0
-                }
         }
 
+	
  	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
         console_init();
@@ -379,13 +241,18 @@ void amd64_main(unsigned long bist)
 	report_bist_failure(bist);
 
         setup_s4882_resource_map();
-	
+
 	needs_reset = setup_coherent_ht_domain();
 	
 #if CONFIG_LOGICAL_CPUS==1
         // It is said that we should start core1 after all core0 launched
+	wait_all_core0_started();
         start_other_cores();
 #endif
+
+        wait_all_aps_started(bsp_apicid);
+
+	// automatically set that for you, but you might meet tight space
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
@@ -393,94 +260,17 @@ void amd64_main(unsigned long bist)
                	soft_reset();
        	}
 
+        allow_all_aps_stop(bsp_apicid);
+
+        nodes = get_nodes();
+        //It's the time to set ctrl now;
+        fill_mem_ctrl(nodes, ctrl, spd_addr);
+	
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(nodes, ctrl);
 
-#if 1
+	post_cache_as_ram(cpu_reset);
-        {
-        /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
-        unsigned v_esp;
-        __asm__ volatile (
-                "movl   %%esp, %0\n\t"
-                : "=a" (v_esp)
-        );
-#if CONFIG_USE_INIT
-        printk_debug("v_esp=%08x\r\n", v_esp);
-#else           
-        print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
-#endif    
-        }
-#endif
-
-#if 1
-
-
-cpu_reset_x:
-
-#if CONFIG_USE_INIT
-        printk_debug("cpu_reset = %08x\r\n",cpu_reset);
-#else
-        print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
-#endif
-
-	if(cpu_reset == 0) {
-	        print_debug("Clearing initial memory region: ");
-	}
-	print_debug("No cache as ram now - ");
-
-	/* store cpu_reset to ebx */
-        __asm__ volatile (
-                "movl %0, %%ebx\n\t"
-                ::"a" (cpu_reset)
-        );
-
-	if(cpu_reset==0) {
-#define CLEAR_FIRST_1M_RAM 1
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-	else {
-#undef CLEAR_FIRST_1M_RAM 
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-
-	__asm__ volatile (
-                /* set new esp */ /* before _RAMBASE */
-                "subl   %0, %%ebp\n\t"
-                "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
-	);
-
-	{
-		unsigned new_cpu_reset;
-
-		/* get back cpu_reset from ebx */
-		__asm__ volatile (
-			"movl %%ebx, %0\n\t"
-			:"=a" (new_cpu_reset)
-		);
-
-		print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
-		if(new_cpu_reset==0) {        
-		        print_debug("done\r\n");	
-		} else 
-		{	
-			print_debug("\r\n");
-		}
-
-#if CONFIG_USE_INIT
-                printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
-#else
-                print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
-#endif
-		/*copy and execute linuxbios_ram */
-		copy_and_run(new_cpu_reset);
-		/* We will not return */
-	}
-#endif
-
-
-	print_debug("should not be here -\r\n");
 
 }