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soc/intel/alderlake/romstage: Fix compilation issue 

Refer to commit 490546f (soc/intel: rename get_prmrr_size) for details.

Change-Id: I4a83feedcdb337ba9613a07215196bc223fb46d1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45651
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2020-09-23 17:46:11 +05:30
parent 32be9f9045
commit 80835a10e1
1 changed files with 1 additions and 1 deletions
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src/soc/intel/alderlake/romstage/fsp_params.c
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@ -53,7 +53,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
sizeof(config->PcieClkSrcClkReq));
m_cfg->PrmrrSize = get_prmrr_size();
m_cfg->PrmrrSize = get_valid_prmrr_size();
m_cfg->EnableC6Dram = config->enable_c6dram;
/* Disable BIOS Guard */
m_cfg->BiosGuard = 0;