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drivers/intel/fsp1_1: Remove verstage compilation units 

Only SOC_INTEL_BRASWELL is using FSP1.1. It has too little CAR
available set up by FSP-T to have VBOOT_STARTS_IN_BOOTBLOCK and
therefore verstage is not possible either.

Change-Id: I54361c835055907c2a4414ec26a1495425d4ef09
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52785
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2021-04-30 15:10:52 +02:00 committed by Felix Held
parent f25f0954c3
commit 808c950566
2 changed files with 0 additions and 15 deletions
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4
src/drivers/intel/fsp1_1/Makefile.inc
View File

@ -2,10 +2,6 @@
ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y) ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y)
verstage-y += car.c
verstage-y += fsp_util.c
verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += verstage.c
bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S
bootblock-y += fsp_util.c bootblock-y += fsp_util.c
bootblock-y += ../../../cpu/intel/microcode/microcode_asm.S bootblock-y += ../../../cpu/intel/microcode/microcode_asm.S

11
src/drivers/intel/fsp1_1/verstage.c
View File

@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <fsp/car.h>
#include <program_loading.h>
void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
{
run_romstage();
/* Will actually never return. */
return NULL;
}