From 80b1fa3332a8022a45bfeacb129a2b171cc30135 Mon Sep 17 00:00:00 2001 From: Tim Chu Date: Wed, 14 Dec 2022 11:37:55 +0000 Subject: [PATCH] soc/intel/xeon_sp: Enable FSP_ERROR_INFO_HOB handling After calling FSP MemoryInit API, if there is an error, some FSPs (such as SPR-SP FSP) is capable of generating FSP_ERROR_INFO_HOB. Check existence of such a HOB and handle it accordingly. Signed-off-by: Tim Chu Change-Id: I612393ffac90815606f3f2544bc1518f6912e605 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71952 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- src/soc/intel/xeon_sp/include/soc/romstage.h | 1 + src/soc/intel/xeon_sp/romstage.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h index a2adfed918..10d334ff4d 100644 --- a/src/soc/intel/xeon_sp/include/soc/romstage.h +++ b/src/soc/intel/xeon_sp/include/soc/romstage.h @@ -10,5 +10,6 @@ void mainboard_memory_init_params(FSPM_UPD * mupd); void mainboard_rtc_failed(void); void save_dimm_info(void); void mainboard_ewl_check(void); +void fsp_check_for_error(void); #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index d001d61ece..530e6eaf0b 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -17,6 +17,9 @@ void mainboard_romstage_entry(void) printk(BIOS_DEBUG, "coreboot fsp_memory_init finished...\n"); mainboard_ewl_check(); + if (CONFIG(ENABLE_FSP_ERROR_INFO)) + fsp_check_for_error(); + unlock_pam_regions(); save_dimm_info();